公开(公告)号：US20230011449A1

公开(公告)日：2023-01-12

申请号：US17863167

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaerin Lee ,  Yang Azevedo Tavares ,  Minjae Lee ,  Kyeongkeun Kang

IPC: H03M1/06

Abstract: An apparatus and a method of correcting a mismatch of a time-interleaved analog-to-digital converter are provided. The apparatus may include: a time-interleaved analog-to-digital converter configured to receive a non-return-to-zero (NRZ) signal in a correction mode and generate a first output signal, and including a plurality of analog-to-digital converters; and a mismatch corrector configured to generate a second output signal by processing the first output signal of the time-interleaved analog-to-digital converter based on parameters, wherein the parameters may be generated based on the first output signal of the time-interleaved analog-to-digital converter in the correction mode, and a period of the NRZ signal may be different from a product of a sampling period of the time-interleaved analog-to-digital converter and a number of the plurality of analog-to-digital converters included in the time-interleaved analog-to-digital converter.

公开(公告)号：US12224759B2

公开(公告)日：2025-02-11

申请号：US17863167

申请日：2022-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaerin Lee ,  Yang Azevedo Tavares ,  Minjae Lee ,  Kyeongkeun Kang

IPC: H03M1/10 ,  H03M1/06

Abstract: An apparatus and a method of correcting a mismatch of a time-interleaved analog-to-digital converter are provided. The apparatus may include: a time-interleaved analog-to-digital converter configured to receive a non-return-to-zero (NRZ) signal in a correction mode and generate a first output signal, and including a plurality of analog-to-digital converters; and a mismatch corrector configured to generate a second output signal by processing the first output signal of the time-interleaved analog-to-digital converter based on parameters, wherein the parameters may be generated based on the first output signal of the time-interleaved analog-to-digital converter in the correction mode, and a period of the NRZ signal may be different from a product of a sampling period of the time-interleaved analog-to-digital converter and a number of the plurality of analog-to-digital converters included in the time-interleaved analog-to-digital converter.

公开(公告)号：US11916565B2

公开(公告)日：2024-02-27

申请号：US17673416

申请日：2022-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaerin Lee ,  Minjae Lee ,  Sewon Lee ,  Kyeongkeun Kang

IPC: H03M1/10

CPC classification number: H03M1/1023

Abstract: An analog-to-digital converter is provided. The analog-to-digital converter includes: a sample/hold circuit; a digital-to-analog converter; a plurality of comparison circuits; a control logic; and a digital register, wherein the plurality of comparison circuits include: a first comparison circuit configured to output a first comparison result signal in a first operation period; a second comparison circuit configured to, in a second operation period, calibrate an offset of a second comparison result signal based on a reference signal corresponding to the first comparison result signal among a plurality of reference signals and output the calibrated second comparison result signal; and a third comparison circuit configured to, in a third operation period, calibrate an offset of a third comparison result signal based on a reference signal corresponding to the calibrated second comparison result signal and output the calibrated third comparison result signal.

公开(公告)号：US11711091B2

公开(公告)日：2023-07-25

申请号：US17675060

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaerin Lee ,  Minjae Lee ,  Hyungyu Ju ,  Kyeongkeun Kang

IPC: H03M1/12 ,  H03M1/50 ,  H03M1/46

CPC classification number: H03M1/1245 ,  H03M1/466 ,  H03M1/50

Abstract: An analog-to-digital converter, including a sample/hold circuit; a reference voltage driver; a digital-to-analog converter; a comparator; and a logic circuit, wherein the reference voltage driver includes: a first voltage supplier circuit configured to output an external supply voltage provided from outside of the analog-to-digital converter; a second voltage supplier circuit configured to output a sampled reference voltage that is obtained during a sampling phase based on control signals received from the logic circuit; and a switching driver configured to electrically connect the first voltage supplier circuit to the digital-to-analog converter during a first conversion phase after the sampling phase based on the control signals received from the logic circuit, and to electrically connect the second voltage supplier circuit to the digital-to-analog converter during a second conversion phase based on the control signals received from the logic circuit.

公开(公告)号：US20220407534A1

公开(公告)日：2022-12-22

申请号：US17675060

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaerin LEE ,  Minjae Lee ,  Hyungyu Ju ,  Kyeongkeun Kang

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/50

Abstract: An analog-to-digital converter, including a sample/hold circuit; a reference voltage driver; a digital-to-analog converter; a comparator; and a logic circuit, wherein the reference voltage driver includes: a first voltage supplier circuit configured to output an external supply voltage provided from outside of the analog-to-digital converter; a second voltage supplier circuit configured to output a sampled reference voltage that is obtained during a sampling phase based on control signals received from the logic circuit; and a switching driver configured to electrically connect the first voltage supplier circuit to the digital-to-analog converter during a first conversion phase after the sampling phase based on the control signals received from the logic circuit, and to electrically connect the second voltage supplier circuit to the digital-to-analog converter during a second conversion phase based on the control signals received from the logic circuit.