公开(公告)号：US20140246726A1

公开(公告)日：2014-09-04

申请号：US14275113

申请日：2014-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon-Joo NA ,  Hyung-Seok HONG ,  Sang-Bom KANG ,  Hyeok-Jun SON ,  June-Hee LEE ,  Jeong-Hee HAN ,  Sang-Jin HYUN

IPC: H01L29/49 ,  H01L27/092

CPC classification number: H01L29/4958 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

Abstract translation: 制造半导体的方法可以包括提供其中限定有第一和第二区域的基板，分别形成层间电介质层，该层间绝缘层包括分别形成在第一和第二区域中的第一和第二沟槽，并沿着顶表面保形地形成栅介电层 层间介质层，第一沟槽和侧面的侧表面和底表面以及第二沟槽的底表面。 可以在栅极介电层上形成蚀刻停止介电层，可以形成第一金属层以填充第一和第二沟槽，并且可以使用蚀刻停止介电层作为蚀刻来去除第一区域中的第一金属层 塞子。