公开(公告)号：US20240128347A1

公开(公告)日：2024-04-18

申请号：US18397700

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu CHO ,  Rak Hwan KIM ,  Hyeok-Jun SON ,  Do Sun LEE ,  Won Keun CHUNG

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4983 ,  H01L21/28132 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

公开(公告)号：US20220285518A1

公开(公告)日：2022-09-08

申请号：US17826380

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu CHO ,  Rak Hwan KIM ,  Hyeok-Jun SON ,  Do Sun LEE ,  Won Keun CHUNG

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L29/786

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

公开(公告)号：US20250107136A1

公开(公告)日：2025-03-27

申请号：US18628220

申请日：2024-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeok-Jun SON ,  Chan Hyeong LEE

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: Provided a semiconductor device. The semiconductor device comprises an active pattern extending in a first direction on a substrate, a gate stack extending in a second direction intersecting the first direction on the active pattern, and a source/drain pattern on at least one side of the gate stack, wherein the gate stack includes a first work function pattern, a second work function pattern on the first work function pattern, and a diffusion prevention pattern between the first work function pattern and the second work function pattern, and wherein a concentration of aluminum in the second work function pattern is greater than a concentration of aluminum in the first work function pattern.

公开(公告)号：US20170005175A1

公开(公告)日：2017-01-05

申请号：US15186982

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol SONG ,  Wandon KIM ,  Hoonjoo NA ,  Suyoung BAE ,  Hyeok-Jun SON ,  Sangjin HYUN

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L27/085

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may he between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括具有共同导电类型的多个有源区和在分离的有源区上分开的相应的栅电极。 不同的高k电介质层可以在分离的有源区和有源区上的相应栅电极之间。 不同数量的高k电介质层可以在分离的有源区域和有源区域上的相应栅电极之间。 不同的高k电介质层可以包括不同的功函调整材料。

公开(公告)号：US20210210613A1

公开(公告)日：2021-07-08

申请号：US17015296

申请日：2020-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nam Gyu CHO ,  Rak Hwan KIM ,  Hyeok-Jun SON ,  Do Sun LEE ,  Won Keun CHUNG

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L21/311 ,  H01L29/66

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.

公开(公告)号：US20180019314A1

公开(公告)日：2018-01-18

申请号：US15717324

申请日：2017-09-27

Applicant: Samsung Electronics Co ., Ltd .

Inventor： Wan-Don Kim ,  Oh-Seong KWON ,  Hoon-Joo NA ,  Hyeok-Jun SON ,  Jae-Yeol SONG ,  Sung-Kee HAN ,  Sang-Jin HYUN

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/4238

Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.

公开(公告)号：US20140246726A1

公开(公告)日：2014-09-04

申请号：US14275113

申请日：2014-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon-Joo NA ,  Hyung-Seok HONG ,  Sang-Bom KANG ,  Hyeok-Jun SON ,  June-Hee LEE ,  Jeong-Hee HAN ,  Sang-Jin HYUN

IPC: H01L29/49 ,  H01L27/092

CPC classification number: H01L29/4958 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

Abstract translation: 制造半导体的方法可以包括提供其中限定有第一和第二区域的基板，分别形成层间电介质层，该层间绝缘层包括分别形成在第一和第二区域中的第一和第二沟槽，并沿着顶表面保形地形成栅介电层 层间介质层，第一沟槽和侧面的侧表面和底表面以及第二沟槽的底表面。 可以在栅极介电层上形成蚀刻停止介电层，可以形成第一金属层以填充第一和第二沟槽，并且可以使用蚀刻停止介电层作为蚀刻来去除第一区域中的第一金属层 塞子。