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    EYE OPENING MEASUREMENT CIRCUIT CALCULATING DIFFERENCE BETWEEN SIGMA LEVELS, RECEIVER INCLUDING THE SAME, AND METHOD FOR MEASURING EYE OPENING
    1.
    发明申请
    EYE OPENING MEASUREMENT CIRCUIT CALCULATING DIFFERENCE BETWEEN SIGMA LEVELS, RECEIVER INCLUDING THE SAME, AND METHOD FOR MEASURING EYE OPENING 审中-公开

    公开(公告)号：US20200064401A1

    公开(公告)日：2020-02-27

    申请号：US16669958

    申请日：2019-10-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： June-Hee LEE ,  Byungwook CHO ,  Bongkyu KIM

    IPC: G01R31/317 ,  H04B1/16

    Abstract: A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

    EYE OPENING MEASUREMENT CIRCUIT CALCULATING DIFFERENCE BETWEEN SIGMA LEVELS, RECEIVER INCLUDING THE SAME, AND METHOD FOR MEASURING EYE OPENING
    2.
    发明申请
    EYE OPENING MEASUREMENT CIRCUIT CALCULATING DIFFERENCE BETWEEN SIGMA LEVELS, RECEIVER INCLUDING THE SAME, AND METHOD FOR MEASURING EYE OPENING 审中-公开

    公开(公告)号：US20190353704A1

    公开(公告)日：2019-11-21

    申请号：US16181241

    申请日：2018-11-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： June-Hee LEE ,  Byungwook CHO ,  Bongkyu KIM

    IPC: G01R31/317 ,  H04B1/16

    Abstract: A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

    ELECTRONIC DEVICE HAVING AUXILIARY BATTERY EMBEDDED THEREIN AND METHOD OF CHARGING AUXILIARY BATTERY
    4.
    发明申请
    ELECTRONIC DEVICE HAVING AUXILIARY BATTERY EMBEDDED THEREIN AND METHOD OF CHARGING AUXILIARY BATTERY 审中-公开
    具有嵌入式辅助电池的电子设备和充电辅助电池的方法

    公开(公告)号：US20160204640A1

    公开(公告)日：2016-07-14

    申请号：US14991029

    申请日：2016-01-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Suk KWAK ,  Myung-Sik KIM ,  Young-Chul KO ,  Chang-Yeong KIM ,  June-Hee LEE ,  So-Won KIM ,  Yang-Wook KIM

    IPC: H02J7/00 ,  H04B1/3883 ,  H04M1/02

    CPC classification number: H02J7/0091 ,  H02J7/0045 ,  H02J7/0054 ,  H02J7/34 ,  H04B1/3883 ,  H04M1/0262 ,  H04M1/72519 ,  H04W52/0296 ,  Y02D70/00

    Abstract: An electronic device is provided including: a display for displaying a UI element; a processor for processing an application; a Printed Board Assembly (PBA) having the processor mounted thereon, and arranged to be substantially parallel to the display; a main battery which supplies power to the electronic device, and is rechargeable and detachable; an auxiliary battery for supplying power to the electronic device; a first frame which houses the main battery, fixes the PBA, and is arranged to be substantially parallel to the display; a second frame for fixing the display and the first frame; and a cover coupled to the second frame, wherein the first frame includes a hole for housing the auxiliary battery, and the electronic device can receive power supplied from the auxiliary battery when power supply from the main battery is terminated.

    Abstract translation: 提供一种电子设备，包括：用于显示UI元素的显示器; 用于处理应用的处理器; 印刷电路板组件（PBA），其上安装有处理器，并且布置成基本上平行于显示器; 主电池，其向电子设备供电，并且是可充电和可拆卸的; 用于向电子设备供电的辅助电池; 容纳主电池的第一框架，固定PBA，并且布置成基本上平行于显示器; 用于固定所述显示器和所述第一框架的第二框架; 以及联接到所述第二框架的盖，其中所述第一框架包括用于容纳所述辅助电池的孔，并且当从所述主电池的电力供应终止时，所述电子设备可以接收从所述辅助电池供应的电力。

    ELECTRONIC DEVICES INCLUDING EQUALIZERS OPERATING BASED ON COEFFICIENTS ADJUSTED IN TRAINING OPERATIONS
    5.
    发明申请
    ELECTRONIC DEVICES INCLUDING EQUALIZERS OPERATING BASED ON COEFFICIENTS ADJUSTED IN TRAINING OPERATIONS 审中-公开

    公开(公告)号：US20190386859A1

    公开(公告)日：2019-12-19

    申请号：US16253589

    申请日：2019-01-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： June-Hee LEE ,  Byungwook CHO ,  Bongkyu KIM ,  Gun-IL KANG

    IPC: H04L25/03

    Abstract: An electronic device includes a reception equalizer that performs, a first equalization on a first signal based on a first coefficient, and one or more second equalizations on one or more second signals based on the first coefficient, the one or more second signals being based on a second coefficient associated with one or more characteristics of a transmission equalizer of the external device, and circuitry that iteratively sends control information generated based on the first coefficient to the external device until a termination condition is satisfied with regard to the first coefficient, the control information causing the second coefficient to be increased or decreased, the iteratively sent control information causing a first absolute value of the first coefficient corresponding to a final equalization of the one or more second equalizations to become smaller than a second absolute value of the first coefficient corresponding to the first equalization.

    CLOCK SWITCH DEVICE AND SYSTEM-ON-CHIP HAVING THE SAME
    6.
    发明申请
    CLOCK SWITCH DEVICE AND SYSTEM-ON-CHIP HAVING THE SAME 有权
    时钟切换装置和具有相同功能的片上系统

    公开(公告)号：US20160041578A1

    公开(公告)日：2016-02-11

    申请号：US14635145

    申请日：2015-03-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： June-Hee LEE ,  Bong-Kyu KIM ,  Dong-Chul CHOI ,  Gun-Il KANG

    IPC: G06F1/10 ,  G06F1/12 ,  G06F13/40

    CPC classification number: G06F1/10 ,  G06F1/12 ,  G06F1/14 ,  G06F13/4022

    Abstract: A clock switch device includes a controller and a switching circuit. The controller sets a clock switch period using a control signal when a logic level of a mode signal is changed. The switching circuit receives a first clock signal, a second clock signal and an auxiliary clock signal. The switching circuit, based on the control signal, outputs one clock signal between the first clock signal and the second clock signal as a glitch free clock signal before the clock switch period, stops outputting the one clock signal and outputs the auxiliary clock signal as the glitch free clock signal during the clock switch period, and stops outputting the auxiliary clock signal and outputs another clock signal between the first clock signal and the second clock signal as the glitch free clock signal after the clock switch period.

    Abstract translation: 时钟切换装置包括控制器和开关电路。 当模式信号的逻辑电平改变时，控制器使用控制信号设置时钟切换周期。 开关电路接收第一时钟信号，第二时钟信号和辅助时钟信号。 开关电路基于控制信号，在时钟切换期间之前，将第一时钟信号和第二时钟信号之间的一个时钟信号作为无毛刺时钟信号输出，停止输出一个时钟信号，并输出辅助时钟信号 在时钟切换期间内无毛刺时钟信号，停止输出辅助时钟信号，并在第一时钟信号和第二时钟信号之间输出另一个时钟信号作为时钟切换周期后的无毛刺时钟信号。

    METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES USING ETCH STOP DIELECTRIC LAYERS AND RELATED DEVICES
    8.
    发明申请
    METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICES USING ETCH STOP DIELECTRIC LAYERS AND RELATED DEVICES 审中-公开
    使用蚀刻介质层和相关器件制造半导体器件的方法

    公开(公告)号：US20140246726A1

    公开(公告)日：2014-09-04

    申请号：US14275113

    申请日：2014-05-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoon-Joo NA ,  Hyung-Seok HONG ,  Sang-Bom KANG ,  Hyeok-Jun SON ,  June-Hee LEE ,  Jeong-Hee HAN ,  Sang-Jin HYUN

    IPC: H01L29/49 ,  H01L27/092

    CPC classification number: H01L29/4958 ,  H01L21/82345 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

    Abstract: A method for manufacturing a semiconductor may include providing a substrate having first and second regions defined therein, forming an interlayer dielectric layer including first and second trenches formed in the first and second regions, respectively, and conformally forming a gate dielectric layer along a top surface of the interlayer dielectric layer, side and bottom surfaces of the first trench and side, and bottom surfaces of the second trench. An etch stop dielectric layer may be formed on the gate dielectric layer, a first metal layer may be formed to fill the first and second trenches, and the first metal layer in the first region may be removed using the etch stop dielectric layer as an etch stopper.

    Abstract translation: 制造半导体的方法可以包括提供其中限定有第一和第二区域的基板，分别形成层间电介质层，该层间绝缘层包括分别形成在第一和第二区域中的第一和第二沟槽，并沿着顶表面保形地形成栅介电层 层间介质层，第一沟槽和侧面的侧表面和底表面以及第二沟槽的底表面。 可以在栅极介电层上形成蚀刻停止介电层，可以形成第一金属层以填充第一和第二沟槽，并且可以使用蚀刻停止介电层作为蚀刻来去除第一区域中的第一金属层 塞子。

    SIGNAL RECEIVING CIRCUIT AND OPERATION METHOD THEREOF
    9.
    发明申请
    SIGNAL RECEIVING CIRCUIT AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190386775A1

    公开(公告)日：2019-12-19

    申请号：US16257249

    申请日：2019-01-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： June-Hee LEE ,  Donghyuk LIM

    IPC: H04L1/00 ,  H04L25/03 ,  H03M13/41 ,  H03M13/00

    Abstract: A signal receiving circuit may include a receiving equalizer and a sequence estimator. The receiving equalizer may be configured to compensate an inter-symbol interference in a signal from an external to output an equalization data, based on a receiving signal from an outside. The sequence estimator may be configured to determine a termination symbol, based on the equalization data, to perform a decoding on the receiving signal, based on the determined termination symbol, and to output the decoded receiving signal as a sequence data.

    HYBRID CLOCK AND DATA RECOVERY CIRCUIT AND SYSTEM INCLUDING THE SAME
    10.
    发明申请
    HYBRID CLOCK AND DATA RECOVERY CIRCUIT AND SYSTEM INCLUDING THE SAME 有权
    混合时钟和数据恢复电路及其系统

    公开(公告)号：US20160013927A1

    公开(公告)日：2016-01-14

    申请号：US14489986

    申请日：2014-09-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： June-Hee LEE ,  Jongshin SHIN ,  Youngkyun JEONG ,  Dongchul CHOI

    IPC: H04L7/033 ,  H04L27/22

    CPC classification number: H04L7/033 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H04L27/22

    Abstract: A clock data recovery circuit includes a sampler to sample incoming data bits, a phase detector to generate an edge position signal and a polarity signal based on the sampled incoming data, a finite state machine to save a current edge position state, a polarity decision unit to generate a polarity inversion signal to invert the polarity signal, a gain controller to generate a tracking bandwidth signal, a recovery loop configured to adjust an edge offset of the reference clock, and a bit selector configured to recover the incoming data. The clock data recovery circuit has a first latency at a first operation mode and a second latency at a second operation mode. The phase detector in the clock data recovery circuit may include a first phase detector and a second detector combined together for a low latency and low lock time of the clock data recovery circuit.

    Abstract translation: 时钟数据恢复电路包括：采样器，用于对输入的数据位进行采样;相位检测器，用于根据采样的输入数据产生边沿位置信号和极性信号;有限状态机，用于保存当前边沿位置状态;极性判定单元 产生极性反转信号以反转极性信号，增益控制器产生跟踪带宽信号;恢复环路，被配置为调整参考时钟的边沿偏移;以及位选择器，被配置为恢复输入数据。 时钟数据恢复电路在第一操作模式下具有第一等待时间，在第二操作模式下具有第二等待时间。 时钟数据恢复电路中的相位检测器可以包括第一相位检测器和第二检测器，其组合在一起，用于时钟数据恢复电路的低等待时间和低锁定时间。

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