公开(公告)号：US20230005853A1

公开(公告)日：2023-01-05

申请号：US17674974

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kunsang PARK ,  Kyuha LEE ,  Youngmin LEE ,  Seokho KIM ,  Inyoung LEE ,  Seokhwan JEONG ,  Sungdong CHO

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66

Abstract: A semiconductor package includes a first structure having a first insulating layer and a first bonding pad penetrating the first insulating layer, and a second structure on the first structure and having a second insulating layer bonded to the first insulating layer, a bonding pad structure penetrating the second insulating layer and bonded to the first bonding pad, and a test pad structure penetrating the second insulating layer and including a test pad in an opening penetrating the second insulating layer and having a protrusion with a flat surface, and a bonding layer filling the opening and covering the test pad and the flat surface, the protrusion of the test pad extending from a surface in contact with the bonding layer, and the flat surface of the protrusion being within the opening and spaced apart from an interface between the bonding layer and the first insulating layer.

公开(公告)号：US20220208706A1

公开(公告)日：2022-06-30

申请号：US17694035

申请日：2022-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joohee JANG ,  Seokho KIM ,  Hoonjoo NA ,  Jaehyung PARK ,  Kyuha LEE

IPC: H01L23/00 ,  H01L27/146

Abstract: A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

公开(公告)号：US20220199670A1

公开(公告)日：2022-06-23

申请号：US17409888

申请日：2021-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongyoung JANG ,  Seokho KIM ,  Eungkyu LEE

IPC: H01L27/146 ,  H01L23/00

Abstract: An image sensor includes a sensor chip and a logic chip. The sensor chip includes a first substrate, an upper bonding layer, a first wiring layer, and the logic chip includes a second substrate, a lower bonding layer, a second wiring layer. The upper and lower bonding layers contact each other, with the upper bonding layer including an upper dielectric layer, an upper conductive pad, an upper shield structure, and an upper wiring line, and the lower bonding layer including a lower dielectric layer, a lower conductive pad, a lower shield structure, and a lower wiring line. The upper wiring line, upper conductive pad, and upper shield structure being one body, and the lower wiring line, lower conductive pad, and lower shield structure being one body, the upper and lower conductive pads overlap and contact each other, and the upper and lower wiring lines overlap and contact each other.

公开(公告)号：US20220093567A1

公开(公告)日：2022-03-24

申请号：US17376784

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinnam KIM ,  Seokho KIM ,  Hoonjoo NA ,  Kwangjin MOON

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a first structure including a first semiconductor chip, and a second structure on the first structure. The second structure includes a second semiconductor chip, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating gap fill pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures. At least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern.

公开(公告)号：US20220020624A1

公开(公告)日：2022-01-20

申请号：US17218606

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyun PHEE ,  Hoechul KIM ,  Seokho KIM ,  Taeyeong KIM ,  Hoonjoo NA

IPC: H01L21/68 ,  H01L21/67

Abstract: A wafer bonding apparatus including a first stage having a first surface and being configured to hold a first wafer on the first surface; a second stage having a second surface and being configured to hold a second wafer on the second surface facing the first surface; a first target image sensor on an outer portion of the first stage; a second target image sensor on an outer portion of the second stage; and a target portion on the first or second stage, the target portion having a target plate fixedly installed and spaced apart from the first or second target image sensor by a predetermined distance, wherein, in an alignment measurement of the first and second stages, the first and second stages are movable so that the first and second target image sensors face each other and the target plate is between the first and second target image sensors.