公开(公告)号：US10553264B2

公开(公告)日：2020-02-04

申请号：US15723532

申请日：2017-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00 ,  G11C7/22 ,  G06F13/16 ,  G11C7/10

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US20150155029A1

公开(公告)日：2015-06-04

申请号：US14325852

申请日：2014-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Chul Kim ,  Yang-Ki Kim ,  Seong-Hwan Jeon

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C7/04 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4076 ,  G11C2207/104 ,  G11C2211/4065

Abstract: A semiconductor memory device that includes a command decoder, a refresh controller, an oscillator and a delay unit. The command decoder generates a self refresh command, and the oscillator generates an oscillation signal. The refresh controller generates a refresh control signal and a recovery signal in response to the self refresh command and the oscillation signal. The delay unit transitions internal nodes included in the delay unit that are not transitioned during a refresh period in response to the refresh control signal and the recovery signal.

Abstract translation: 一种半导体存储器件，包括命令解码器，刷新控制器，振荡器和延迟单元。 命令解码器产生自刷新命令，振荡器产生振荡信号。 刷新控制器响应于自刷新命令和振荡信号产生刷新控制信号和恢复信号。 响应于刷新控制信号和恢复信号，延迟单元转换延迟单元中包括的内部节点，其在刷新周期期间未被转换。