公开(公告)号：US10283186B2

公开(公告)日：2019-05-07

申请号：US15787101

申请日：2017-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-Hwan Jeon ,  Kyung-Soo Ha ,  Jin-Seok Heo ,  In-Dal Song ,  Jung-Hwan Choi

IPC: G11C11/24 ,  G11C11/402 ,  G11C7/22 ,  G11C11/22 ,  G11C7/10 ,  G11C11/4093

Abstract: A data alignment circuit of a semiconductor memory device including: a data sampling circuit configured to receive a data sequence and an internal data strobe signal, wherein the data sampling circuit samples the data sequence based on the internal data strobe signal to generate first and second data sequences; a division circuit configured to receive a clock signal and the internal data strobe signal, divide the clock signal to produce a divided clock signal and output an alignment control signal by sampling the divided clock signal based on the internal data strobe signal; and a data alignment block configured to receive the first and second data sequences, and the alignment control signal, and align the first and second data sequences in parallel to output internal data.

公开(公告)号：US12057193B2

公开(公告)日：2024-08-06

申请号：US18111925

申请日：2023-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G11C7/222 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2254

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US11615825B2

公开(公告)日：2023-03-28

申请号：US17588566

申请日：2022-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US10692555B2

公开(公告)日：2020-06-23

申请号：US16249594

申请日：2019-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok Oh ,  Seong-Hwan Jeon

IPC: G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4076 ,  G11C29/12 ,  G11C29/02 ,  G11C29/10 ,  G11C8/12

Abstract: A method of operating a semiconductor memory device including a plurality of pins configured to transfer data and signals from/to an outside of the semiconductor memory device, a memory cell array and a control logic circuit to control access to the memory cell array. A write command synchronized with a main clock signal and data synchronized with a data clock signal are received from outside of the semiconductor memory device, the data is stored in the memory cell array based on a frequency-divided data clock signal, data is read from the memory cell array in response to a read command and a target address received from the outside of the semiconductor memory device, and the read data is transmitted to the outside of the semiconductor memory device selectively with a strobe signal generated based on a frequency of the main clock signal.

公开(公告)号：US20180102151A1

公开(公告)日：2018-04-12

申请号：US15723532

申请日：2017-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G11C7/22 ,  G06F13/16 ,  G06F1/12 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2254

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US09281048B2

公开(公告)日：2016-03-08

申请号：US14325852

申请日：2014-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Chul Kim ,  Yang-Ki Kim ,  Seong-Hwan Jeon

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4067 ,  G11C7/04

CPC classification number: G11C11/40615 ,  G11C7/04 ,  G11C11/406 ,  G11C11/4067 ,  G11C11/4076 ,  G11C2207/104 ,  G11C2211/4065

Abstract: A semiconductor memory device that includes a command decoder, a refresh controller, an oscillator and a delay unit. The command decoder generates a self refresh command, and the oscillator generates an oscillation signal. The refresh controller generates a refresh control signal and a recovery signal in response to the self refresh command and the oscillation signal. The delay unit transitions internal nodes included in the delay unit that are not transitioned during a refresh period in response to the refresh control signal and the recovery signal.

Abstract translation: 一种半导体存储器件，包括命令解码器，刷新控制器，振荡器和延迟单元。 命令解码器产生自刷新命令，振荡器产生振荡信号。 刷新控制器响应于自刷新命令和振荡信号产生刷新控制信号和恢复信号。 响应于刷新控制信号和恢复信号，延迟单元转换延迟单元中包括的内部节点，其在刷新周期期间未被转换。

公开(公告)号：US11282555B2

公开(公告)日：2022-03-22

申请号：US17190656

申请日：2021-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US10186309B2

公开(公告)日：2019-01-22

申请号：US15624491

申请日：2017-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok Oh ,  Seong-Hwan Jeon

IPC: G11C8/00 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/52 ,  G11C7/10 ,  G06F11/10 ,  G11C29/02 ,  G11C29/04

Abstract: In a method of operating a semiconductor memory device including a memory cell array and a control logic circuit configured to control access to the memory cell array, data synchronized with a differential data clock signal is received from an external memory controller, the data is stored in the memory cell array based on a frequency-divided data clock signal from which the differential data clock signal is divided, data is read from the memory cell array in response to a read command and a target address from the memory controller, and the read data is transmitted to the memory controller with one of a single strobe signal and a differential strobe signal according to a strobe mode of the semiconductor memory device.

公开(公告)号：US09245605B2

公开(公告)日：2016-01-26

申请号：US14250460

申请日：2014-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seong-Hwan Jeon ,  Yang-Ki Kim ,  Seok-Hun Hyun ,  Jung-Hwan Choi

IPC: G11C8/18 ,  G11C7/22 ,  H03L7/081 ,  H03L7/095 ,  H03L7/10

CPC classification number: G11C8/18 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/095 ,  H03L7/10

Abstract: A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state.

Abstract translation: 时钟同步电路包括延迟锁定环（DLL）和延迟锁定控制单元。 DLL被配置为通过将输入时钟信号延迟延迟时间来产生输出时钟信号，并且执行延迟锁定操作，其中延迟时间根据输出时钟信号和 输入时钟信号。 所述延迟锁定控制单元被配置为检测所述DLL的锁定状态，并且基于所确定的锁定状态来控制所述DLL。

公开(公告)号：US10943630B2

公开(公告)日：2021-03-09

申请号：US16731769

申请日：2019-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.