公开(公告)号：US20240023326A1

公开(公告)日：2024-01-18

申请号：US17977575

申请日：2022-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Seungchan YUN ,  Jaehong LEE ,  Kang-ill SEO

IPC: H01L27/112

CPC classification number: H01L27/11206

Abstract: Provided is a multi-stack nanosheet structure that includes: at least a first nanosheet structure and at least a second nanosheet structure, above the substrate, separated from each other, wherein the first nanosheet structure and second nanosheet structure are adjacent to each other; a channel structure comprising a first portion on the first nanosheet structure, a second portion on the second nanosheet structure, and a third portion on the substrate between the first and second portions, wherein the first portion, the second portion and the third portion form a single continuous structure; a gate structure between the first and second portions on the third portion of the channel structure, wherein the gate structure comprises a gate dielectric layer comprising oxide; and at least a first source/drain region on the first nanosheet structure, and at least a second source/drain region on the second nanosheet structure, wherein the first source/drain region and the second source/drain region include an n-type or p-type dopant.

公开(公告)号：US20230352529A1

公开(公告)日：2023-11-02

申请号：US17965551

申请日：2022-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gunho JO ,  Byounghak HONG ,  Seungchan YUN ,  Jaejik BAEK

IPC: H01L29/06 ,  H01L27/06 ,  H01L29/786 ,  H01L25/11 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L27/0688 ,  H01L29/78696 ,  H01L25/117 ,  H01L21/823431

Abstract: Provided is a multi-stack semiconductor device that includes: a lower nanosheet transistor including a plurality of lower channel layers surrounded by a gate structure; and an upper nanosheet transistor stacked on the lower nanosheet transistor and including a plurality of upper channel layers surrounded by the gate structure, wherein the lower channel layers have a smaller channel interval than the upper channel layers.

公开(公告)号：US20210193834A1

公开(公告)日：2021-06-24

申请号：US17038020

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Donghwan HAN

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L27/06

Abstract: A semiconductor device includes a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction, a first gate structure surrounding the plurality of channel layers, first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers and spaced apart from each other in a second direction, an element isolation layer disposed on an upper portion of the first gate structure, a semiconductor layer disposed on the element isolation layer and having a vertical region extending in the first direction and including second source/drain regions spaced apart from each other in the first direction, and a second gate structure disposed to surround a portion of the vertical region. The semiconductor device further includes first to fourth contact plugs.