公开(公告)号：US20240203882A1

公开(公告)日：2024-06-20

申请号：US18197381

申请日：2023-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongjin LEE ,  Jaejik BAEK ,  Myunghoon JUNG ,  Kang-ill SEO

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Provided is a method of manufacturing an integrated circuit device. The method includes forming a semiconductor device, wherein the semiconductor device has one or more source/drain structures, one or more channel structures and wherein the substrate is on a first side of the semiconductor device. The method also includes forming a back-end-of-line (BEOL) region and forming a bottle-neck shaped backside contact structure in the substrate and in contact with a first source/drain structure of the semiconductor device, wherein the bottle-neck shaped backside contact structure has a first side contacting the first source/drain structure, a second side contacting a backside power rail, and sidewalls extending from the first source/drain structure to the backside power rail; and wherein the backside contact structure has a first region having a positive slope and a second region, adjacent to the first region, having no slope.

公开(公告)号：US20230352529A1

公开(公告)日：2023-11-02

申请号：US17965551

申请日：2022-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gunho JO ,  Byounghak HONG ,  Seungchan YUN ,  Jaejik BAEK

IPC: H01L29/06 ,  H01L27/06 ,  H01L29/786 ,  H01L25/11 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L27/0688 ,  H01L29/78696 ,  H01L25/117 ,  H01L21/823431

Abstract: Provided is a multi-stack semiconductor device that includes: a lower nanosheet transistor including a plurality of lower channel layers surrounded by a gate structure; and an upper nanosheet transistor stacked on the lower nanosheet transistor and including a plurality of upper channel layers surrounded by the gate structure, wherein the lower channel layers have a smaller channel interval than the upper channel layers.

公开(公告)号：US20230343839A1

公开(公告)日：2023-10-26

申请号：US17885237

申请日：2022-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Sung KIM ,  Jaejik BAEK ,  Wonhyuk HONG ,  Myunghoon JUNG ,  Jongjin LEE ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/40

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L29/401 ,  H01L29/0673

Abstract: Provided is a semiconductor device that includes: at least one transistor, a front side structure, and a back side structure, the front side structure being disposed opposite to the back side structure with respect to the transistor; and a front via formed at a side of the transistor and connecting the front side structure to the back side structure, wherein the front via is formed in a via hole formed of a lower via hole and an upper via hole vertically connected to each other, and wherein the via hole has a bent structure at a side surface thereof where the lower via hole is connected to the upper via hole.

公开(公告)号：US20230343845A1

公开(公告)日：2023-10-26

申请号：US17891777

申请日：2022-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak HONG ,  Gunho JO ,  Seungchan YUN ,  Jaejik BAEK

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/786 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/78696 ,  H01L29/41775 ,  H01L29/0673 ,  H01L21/823412 ,  H01L21/823437

Abstract: Provided is a multi-stack semiconductor device that includes: a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower gate dielectric layer, a lower work-function metal layer and a lower gate metal pattern; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper gate dielectric layer, an upper work-function metal layer and an upper gate metal pattern, wherein a channel width of the upper channel structure is smaller than a channel width of the lower channel structure, and wherein a replacement metal gate (RMG) inner spacer is formed between the lower work-function metal layer and the upper work-function metal layer at regions where the lower channel structure is not vertically overlapped by the upper channel structure.

公开(公告)号：US20230343823A1

公开(公告)日：2023-10-26

申请号：US17882203

申请日：2022-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaejik BAEK ,  Byounghak Hong ,  Inchan Hwang ,  Kang-ill Seo

IPC: H01L27/06 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/78696

Abstract: Provided is a multi-stack semiconductor device including: a substrate; a lower nanosheet transistor including a lower channel structure; a lower gate structure surrounding the lower channel structure and including a gate dielectric layer; lower source/drain regions at both ends of the lower channel structure; and at least one lower inner spacer isolating the lower source/drain regions from the lower gate structure; an upper nanosheet transistor, on the lower nanosheet transistor, including an upper channel structure; an upper gate structure surrounding the upper channel structure and including the gate dielectric layer; upper source/drain regions at both ends of the upper channel structure; and at least one upper inner spacer isolating the upper source/drain regions from the upper gate structure; and an isolation structure between the lower and upper channel structures, wherein a spacer structure including a same material forming the lower or upper inner spacer is formed at a side of the isolation structure.