公开(公告)号：US20190096791A1

公开(公告)日：2019-03-28

申请号：US15876227

申请日：2018-01-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Puu Jeng ,  Dai-Jang Chen ,  Hsiang-Tai Lu ,  Hsien-Wen Liu ,  Chih-Hsien Lin ,  Shih-Ting Hung ,  Po-Yao Chuang

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373

CPC分类号： H01L23/49822 ,  H01L21/56 ,  H01L22/14 ,  H01L22/32 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/81 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2924/15311 ,  H01L2924/1533

摘要： Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

公开(公告)号：US20180350715A1

公开(公告)日：2018-12-06

申请号：US15964128

申请日：2018-04-27

申请人： HS Elektronik Systeme GmbH

发明人： Richard SINNING ,  Bernd LOEFFLAD ,  Markus GREITHER ,  Peter BRANTL ,  Josef MAIER ,  Rainer SEIDEL

IPC分类号： H01L23/373 ,  H01L23/467

CPC分类号： H01L23/62 ,  H01L24/48 ,  H01L25/071 ,  H01L25/074 ,  H01L25/117 ,  H01L25/16 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/00014

摘要： The present invention relates to a power semiconductor chip module, comprising a substrate having a top side and a bottom side; at least one first power semiconductor device attached to the top side of the substrate; at least one first conductive structure thermally and electrically connecting the first power semiconductor device to the top side of the substrate; at least one second power semiconductor device attached to the bottom side of the substrate; and at least one second conductive structure connecting the second power semiconductor device to the bottom side of the substrate.

公开(公告)号：US20180308827A1

公开(公告)日：2018-10-25

申请号：US15957561

申请日：2018-04-19

申请人： Infineon Technologies AG

发明人： Matthias Wissen ,  Daniel Domes ,  Andreas Groove

IPC分类号： H01L25/10 ,  H01L23/492 ,  H01L23/52 ,  H01L23/367

CPC分类号： H01L25/105 ,  H01L23/3675 ,  H01L23/4922 ,  H01L23/52 ,  H01L25/115 ,  H01L25/117 ,  H05K1/0216

摘要： A power semiconductor arrangement includes a plurality of half-bridges arranged in parallel alongside one another by way of a longer longitudinal side of the half-bridges. An input load current terminal, an output load current terminal and a phase terminal are arranged on a top side of each of the half-bridges, the input load current terminals and the output load current terminals being arranged on an imaginary line that runs orthogonal to the longer longitudinal side of the half-bridges. First connection plates are connected to respective ones of the output load current terminals, and second connection plates are connected to respective ones of the input load current terminals. The first connection plates are arranged above the second connection plates. The first and the second connection plates are arranged in parallel with one another and electrically insulated from one another.

公开(公告)号：US20180233491A1

公开(公告)日：2018-08-16

申请号：US15954326

申请日：2018-04-16

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Jinchang ZHOU ,  Yusheng LIN ,  Mingjiao LIU

IPC分类号： H01L25/07 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/11 ,  H01L25/00 ,  H01L29/739 ,  H01L41/083

CPC分类号： H01L25/071 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/074 ,  H01L25/117 ,  H01L25/50 ,  H01L29/7395 ,  H01L41/083 ,  H01L2224/0401 ,  H01L2224/05085 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/92242 ,  H01L2225/06503 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19105

摘要： A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

公开(公告)号：US10014283B1

公开(公告)日：2018-07-03

申请号：US15782239

申请日：2017-10-12

申请人： Jing Qiao Corporation Limited

发明人： Chin-Liang Chiang ,  Neng-Huang Chu ,  Yi-Lun Wu

IPC分类号： H01L25/065 ,  H01L23/367 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L23/495 ,  H01L23/522 ,  H01L23/15 ,  H01L21/60 ,  H01L21/603 ,  H01L25/04 ,  H01L25/11 ,  H01L25/075

CPC分类号： H01L25/0657 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/52 ,  H01L21/563 ,  H01L23/13 ,  H01L23/15 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/4952 ,  H01L23/5226 ,  H01L23/5385 ,  H01L25/043 ,  H01L25/0756 ,  H01L25/117 ,  H01L2021/60022 ,  H01L2021/60277 ,  H01L2021/603 ,  H01L2224/16225

摘要： The present invention provides a semiconductor device including a first glass substrate, a first integrated chip, a first anisotropic conductive film, a second glass substrate, a second integrated chip, a second anisotropic conductive film, and a packaging body.

公开(公告)号：US20180130721A1

公开(公告)日：2018-05-10

申请号：US15866853

申请日：2018-01-10

申请人： DENSO CORPORATION

发明人： Yasuhiro MIZUNO ,  Isao TAMADA ,  Tomohiro SHIMAZU ,  Hiroshi HAMADA ,  Yuusuke TAKAGI ,  Eiji NAKAGAWA

IPC分类号： H01L23/473 ,  H01L23/367 ,  H01L25/11 ,  H01L25/07 ,  H01L23/40 ,  F28F9/26 ,  F28F3/08 ,  H01L25/18

CPC分类号： H01L23/473 ,  F28D1/0333 ,  F28D1/05308 ,  F28D1/05358 ,  F28F3/086 ,  F28F9/0075 ,  F28F9/0131 ,  F28F9/26 ,  F28F2225/04 ,  H01L23/3675 ,  H01L23/40 ,  H01L25/07 ,  H01L25/074 ,  H01L25/117 ,  H01L25/18 ,  H01L2924/0002 ,  H05K7/20927 ,  H01L2924/00

摘要： A stacked cooler includes flow pipes that are stacked, each of the flow pipes having a flat shape and including a medium passage in which a heat medium flows, a heat exchange object that is disposed between each adjacent two of the flow pipes and is clamped between their flat planes, a protruding pipe part that is connected to at least one of the flow pipes and protrudes in a stacking direction of the flow pipes, and a load restraining part that restrains a load applied to a connection portion of the at least one of the flow pipes to the protruding pipe part as compared with a load applied to the other portion of the at least one of the flow pipes.

公开(公告)号：US20180114785A1

公开(公告)日：2018-04-26

申请号：US15837774

申请日：2017-12-11

申请人： International Business Machines Corporation

发明人： Russell A. Budd ,  Mounir Meghelli ,  Jason Scott Orcutt ,  Jean-Olivier Plouchart

IPC分类号： H01L25/16 ,  H01S5/183 ,  G02B6/122 ,  G02B6/124 ,  G02B6/132 ,  G02B6/34 ,  G02B6/42 ,  H01L21/48 ,  H01S5/10 ,  H01S5/024 ,  H01S5/022 ,  H01S5/02 ,  H01L27/12 ,  H01L25/00 ,  H01L25/11 ,  H01L23/58 ,  H01L23/498 ,  H01L23/485 ,  H01L23/367 ,  H01L21/84 ,  G02B6/12 ,  H01S5/026

CPC分类号： H01L25/167 ,  G02B6/122 ,  G02B6/1221 ,  G02B6/124 ,  G02B6/132 ,  G02B6/34 ,  G02B6/4204 ,  G02B6/4214 ,  G02B6/4274 ,  G02B6/428 ,  G02B2006/12061 ,  G02B2006/12069 ,  G02B2006/12123 ,  G02B2006/12147 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/84 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/485 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/585 ,  H01L25/117 ,  H01L25/50 ,  H01L27/1203 ,  H01L2223/58 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/02248 ,  H01S5/02272 ,  H01S5/02469 ,  H01S5/026 ,  H01S5/1032 ,  H01S5/105 ,  H01S5/18341 ,  H01S5/18361 ,  H01S5/1838

摘要： Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

公开(公告)号：US09941187B2

公开(公告)日：2018-04-10

申请号：US15303628

申请日：2015-04-10

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Tadafumi Yoshida

IPC分类号： H01L23/34 ,  H01L23/40 ,  H01L23/473 ,  H01L25/11 ,  H01L21/48 ,  H01L25/00 ,  H02M7/00 ,  H02M7/537

CPC分类号： H01L23/4012 ,  H01L21/4882 ,  H01L23/40 ,  H01L23/473 ,  H01L25/117 ,  H01L25/50 ,  H01L2924/0002 ,  H02M7/003 ,  H02M7/537 ,  H01L2924/00

摘要： A power converter includes a plurality of power cards, a plurality of coolers and a pressure member. Each of the power cards houses a semiconductor element. The plurality of coolers is laminated with the power cards. The cooler includes a body, a gasket and a metal plate. The body is made of resin, and has an opening that is provided in a side surface of the cooler that faces the adjacent power card. A surface on one side of the metal plate is configured to close the opening through the gasket, and the other surface faces the power card. The pressure member is configured to apply a pressure in a laminating direction on a lamination unit. The opening is sealed by the metal plate by pressure applied by the pressure member on the lamination unit.

公开(公告)号：US09935088B2

公开(公告)日：2018-04-03

申请号：US15456758

申请日：2017-03-13

申请人： International Business Machines Corporation

发明人： Russell A. Budd ,  Mounir Meghelli ,  Jason Scott Orcutt ,  Jean-Olivier Plouchart

IPC分类号： G02B6/42 ,  H01L25/16 ,  H01L23/498 ,  H01L27/12 ,  H01S5/022 ,  H01L23/367 ,  H01L21/48 ,  H01L21/84 ,  H01S5/024 ,  G02B6/122 ,  G02B6/124 ,  G02B6/34 ,  H01S5/02 ,  H01L23/485 ,  H01L23/58 ,  H01L25/11 ,  G02B6/132 ,  H01L25/00 ,  G02B6/12 ,  H01S5/026 ,  H01S5/10 ,  H01S5/183

CPC分类号： H01L25/167 ,  G02B6/122 ,  G02B6/1221 ,  G02B6/124 ,  G02B6/132 ,  G02B6/34 ,  G02B6/4204 ,  G02B6/4214 ,  G02B6/4274 ,  G02B6/428 ,  G02B2006/12061 ,  G02B2006/12069 ,  G02B2006/12123 ,  G02B2006/12147 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/84 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/485 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/585 ,  H01L25/117 ,  H01L25/50 ,  H01L27/1203 ,  H01L2223/58 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01S5/021 ,  H01S5/0215 ,  H01S5/02248 ,  H01S5/02272 ,  H01S5/02469 ,  H01S5/026 ,  H01S5/1032 ,  H01S5/105 ,  H01S5/18341 ,  H01S5/18361 ,  H01S5/1838

摘要： Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

公开(公告)号：US09893047B2

公开(公告)日：2018-02-13

申请号：US15490377

申请日：2017-04-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Bing Dang ,  John Knickerbocker

IPC分类号： H01L21/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/683 ,  H01L25/16 ,  H01L25/18 ,  H01L25/075 ,  H01L25/11 ,  H01L25/04 ,  H01L25/07

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/20 ,  H01L24/32 ,  H01L24/81 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L25/167 ,  H01L25/18 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/6677 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/80121 ,  H01L2224/80143 ,  H01L2224/81005 ,  H01L2224/95001 ,  H01L2224/95144 ,  H01L2224/95146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014

摘要： Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5D semiconductor packages.