公开(公告)号：US20190080998A1

公开(公告)日：2019-03-14

申请号：US15936882

申请日：2018-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sidharth Rastogi ,  Subhash KUCHANURI ,  Jae Seok YANG ,  Kwan Young CHUN

IPC: H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes an insulator on a substrate and having opposite first and second sides that each extend along a first direction, a first fin pattern extending from a third side of the insulator along the first direction, a second fin pattern extending from a fourth side of the insulator along the first direction, and a first gate structure extending from the first side of the insulator along a second direction transverse to the first direction. The device further includes a second gate structure extending from the second side of the insulator along the second direction, a third fin pattern overlapped by the first gate structure, spaced apart from the first side of the insulator, and extending along the first direction, and a fourth fin pattern which overlaps the second gate structure, is spaced apart from the second side, and extends in the direction in which the second side extends. An upper surface of the insulator is higher than an upper surface of the first fin pattern and an upper surface of the second fin pattern.

公开(公告)号：US10147684B1

公开(公告)日：2018-12-04

申请号：US15815083

申请日：2017-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Subhash Kuchanuri ,  Sidharth Rastogi ,  Ranjan Rajeev ,  Chul-hong Park ,  Jae-seok Yang

IPC: H01L23/48 ,  H01L23/544 ,  H01L23/485 ,  H03K19/173 ,  G06F17/50

Abstract: An integrated circuit device includes: a pair of reference conductive lines arranged in parallel in a first direction in a first version logic cell and a pair of swap conductive lines arranged in parallel in a second version logic cell, wherein one reference conductive line and one swap conductive line in different wiring tracks of the pair of reference conductive lines and the pair of swap conductive lines have the same planar shape and the same length, and extend to intersect a cell boundary between the first version logic cell and the second version logic cell.