公开(公告)号：US20220336344A1

公开(公告)日：2022-10-20

申请号：US17853625

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sidharth Rastogi ,  Subhash KUCHANURI ,  Jae Seok YANG ,  Kwan Young CHUN

IPC: H01L23/522 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device includes an insulator on a substrate and having opposite first and second sides that each extend along a first direction, a first fin pattern extending from a third side of the insulator along the first direction, a second fin pattern extending from a fourth side of the insulator along the first direction, and a first gate structure extending from the first side of the insulator along a second direction transverse to the first direction. The device further includes a second gate structure extending from the second side of the insulator along the second direction, a third fin pattern overlapped by the first gate structure, spaced apart from the first side of the insulator, and extending along the first direction, and a fourth fin pattern which overlaps the second gate structure, is spaced apart from the second side, and extends in the direction in which the second side extends. An upper surface of the insulator is higher than an upper surface of the first fin pattern and an upper surface of the second fin pattern.

公开(公告)号：US20190198496A1

公开(公告)日：2019-06-27

申请号：US16255519

申请日：2019-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Wook OH ,  Jae Seok YANG ,  Jong Hyun LEE ,  Hyun Jae LEE ,  Sung Wook HWANG

IPC: H01L27/088 ,  H01L27/02 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L27/0886 ,  G06F17/5072 ,  H01L23/528 ,  H01L27/0207

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

公开(公告)号：US20170287909A1

公开(公告)日：2017-10-05

申请号：US15372840

申请日：2016-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Wook OH ,  Jae Seok YANG ,  Jong Hyun LEE ,  Hyun Jae LEE ,  Sung Wook HWANG

IPC: H01L27/088 ,  G06F17/50 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0886 ,  G06F17/5072 ,  H01L23/528 ,  H01L27/0207

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

公开(公告)号：US20240063259A1

公开(公告)日：2024-02-22

申请号：US18499436

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun KIM ,  Jae Seok YANG ,  Hae Wang LEE

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/0649 ,  H01L29/6656 ,  H01L29/42376 ,  H01L27/0924 ,  H01L29/7851 ,  H01L29/6681 ,  H01L29/4916 ,  H01L21/76224

Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

公开(公告)号：US20190080998A1

公开(公告)日：2019-03-14

申请号：US15936882

申请日：2018-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sidharth Rastogi ,  Subhash KUCHANURI ,  Jae Seok YANG ,  Kwan Young CHUN

IPC: H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes an insulator on a substrate and having opposite first and second sides that each extend along a first direction, a first fin pattern extending from a third side of the insulator along the first direction, a second fin pattern extending from a fourth side of the insulator along the first direction, and a first gate structure extending from the first side of the insulator along a second direction transverse to the first direction. The device further includes a second gate structure extending from the second side of the insulator along the second direction, a third fin pattern overlapped by the first gate structure, spaced apart from the first side of the insulator, and extending along the first direction, and a fourth fin pattern which overlaps the second gate structure, is spaced apart from the second side, and extends in the direction in which the second side extends. An upper surface of the insulator is higher than an upper surface of the first fin pattern and an upper surface of the second fin pattern.

公开(公告)号：US20180182758A1

公开(公告)日：2018-06-28

申请号：US15902025

申请日：2018-02-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In Wook OH ,  Jae Seok YANG ,  Jong Hyun LEE ,  Hyun Jae LEE ,  Sung Wook HWANG

IPC: H01L27/088 ,  H01L27/02 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L27/0886 ,  G06F17/5072 ,  H01L23/528 ,  H01L27/0207

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

公开(公告)号：US20220077284A1

公开(公告)日：2022-03-10

申请号：US17526840

申请日：2021-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hun KIM ,  Jae Seok YANG ,  Hae Wang LEE

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

公开(公告)号：US20200098681A1

公开(公告)日：2020-03-26

申请号：US16381243

申请日：2019-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Hun Kim ,  Jae Seok YANG ,  Hae Wang LEE

IPC: H01L23/528 ,  H01L23/532 ,  H01L29/417

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a buried conductive layer disposed adjacent to the active region on the substrate and extending in the first direction, a gate electrode intersecting the active region and extending in a second direction crossing the first direction, a source/drain layer disposed on the active region on one side of the gate electrode, a gate isolation pattern disposed on the buried conductive layer so as to be disposed adjacent to one end of the gate electrode, and extending in the first direction, and a contact plug disposed on the source/drain layer, electrically connected to the buried conductive layer, and in contact with the gate isolation pattern.

公开(公告)号：US20180090492A1

公开(公告)日：2018-03-29

申请号：US15473913

申请日：2017-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rajeev RANJAN ,  Deepak SHARMA ,  Subhash KUCHANURI ,  Chul Hong PARK ,  Jae Seok YANG ,  Kwan Young CHUN

IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L23/522

Abstract: Integrated circuit devices are provided. The IC devices may include an active region extending in a first direction, first and second gate electrodes extending in a second direction, a first impurity region in the active region adjacent a first side of the first gate electrode, a second impurity region in the active region between a second side of the first gate electrode and a first side of the second gate electrode, a third impurity region in the active region adjacent a second side of the second gate electrode, a cross gate contact electrically connecting the first and second impurity regions, a first contact electrically connected to the third impurity region, a first wire electrically connected to the cross gate contact, and a second wire electrically connected to the first contact. The first and second wires may extend only in the first direction and may be on the same line.

公开(公告)号：US20200328147A1

公开(公告)日：2020-10-15

申请号：US16916811

申请日：2020-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sidharth Rastogi ,  Subhash KUCHANURI ,  Jae Seok YANG ,  Kwan Young CHUN

IPC: H01L23/522 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A semiconductor device includes an insulator on a substrate and having opposite first and second sides that each extend along a first direction, a first fin pattern extending from a third side of the insulator along the first direction, a second fin pattern extending from a fourth side of the insulator along the first direction, and a first gate structure extending from the first side of the insulator along a second direction transverse to the first direction. The device further includes a second gate structure extending from the second side of the insulator along the second direction, a third fin pattern overlapped by the first gate structure, spaced apart from the first side of the insulator, and extending along the first direction, and a fourth fin pattern which overlaps the second gate structure, is spaced apart from the second side, and extends in the direction in which the second side extends. An upper surface of the insulator is higher than an upper surface of the first fin pattern and an upper surface of the second fin pattern.