公开(公告)号：US20220123006A1

公开(公告)日：2022-04-21

申请号：US17340148

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ho AHN ,  Ji Won KIM ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Suk Kang SUNG

IPC: H01L27/11556 ,  H01L25/065 ,  H01L27/11582 ,  H01L23/538

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.