公开(公告)号：US20220246643A1

公开(公告)日：2022-08-04

申请号：US17726899

申请日：2022-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho AHN ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Bum Kyu KANG ,  Sang Don LEE

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556

Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

公开(公告)号：US20220115344A1

公开(公告)日：2022-04-14

申请号：US17405637

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Won KIM ,  Jae Ho AHN ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Suk Kang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

公开(公告)号：US20220130782A1

公开(公告)日：2022-04-28

申请号：US17389841

申请日：2021-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho AHN ,  Ji Won KIM ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Suk Kang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/535 ,  H01L21/768 ,  H01L25/00

Abstract: A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

公开(公告)号：US20210111187A1

公开(公告)日：2021-04-15

申请号：US16890115

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Ho AHN ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Bum Kyu KANG ,  Sang Don LEE

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565

Abstract: A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region.

公开(公告)号：US20240064974A1

公开(公告)日：2024-02-22

申请号：US18386639

申请日：2023-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ho AHN ,  Ji Won KIM ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Suk Kang SUNG

IPC: H10B41/27 ,  H01L23/538 ,  H01L25/065 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L23/5384 ,  H01L25/0657 ,  H10B43/27

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

公开(公告)号：US20220123006A1

公开(公告)日：2022-04-21

申请号：US17340148

申请日：2021-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Ho AHN ,  Ji Won KIM ,  Sung-Min HWANG ,  Joon-Sung LIM ,  Suk Kang SUNG

IPC: H01L27/11556 ,  H01L25/065 ,  H01L27/11582 ,  H01L23/538

Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

公开(公告)号：US20220108963A1

公开(公告)日：2022-04-07

申请号：US17323076

申请日：2021-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min HWANG ,  Ji Won KIM ,  Jae Ho AHN ,  Joon-Sung LIM ,  Suk Kang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.