NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

    公开(公告)号:US20220108963A1

    公开(公告)日:2022-04-07

    申请号:US17323076

    申请日:2021-05-18

    Abstract: A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

    NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM INCLUDING THE SAME

    公开(公告)号:US20220115344A1

    公开(公告)日:2022-04-14

    申请号:US17405637

    申请日:2021-08-18

    Abstract: The nonvolatile memory device includes a substrate including a first surface and a second surface opposite to the first surface in a first direction; a common source line on the first surface of the substrate; a plurality of word lines stacked on the common source line; a first insulating pattern spaced apart from the plurality of word lines in a second direction crossing the first direction, and in the substrate; an insulating layer on the second surface of the substrate; a first contact plug penetrating the first insulating pattern and extending in the first direction; a second contact plug penetrating the insulating layer, extending in the first direction, and connected to the first contact plug; an upper bonding metal connected to the first contact plug and connected to a circuit element; and a first input/output pad connected to the second contact plug and electrically connected to the circuit element.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请

    公开(公告)号:US20220028885A1

    公开(公告)日:2022-01-27

    申请号:US17203122

    申请日:2021-03-16

    Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明公开

    公开(公告)号:US20240215245A1

    公开(公告)日:2024-06-27

    申请号:US18595737

    申请日:2024-03-05

    CPC classification number: H10B43/27 H10B41/10 H10B41/27 H10B43/10

    Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

    SEMICONDUCTOR MEMORY DEVICE, ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD FOR FABRICATING THE SAME

    公开(公告)号:US20220130782A1

    公开(公告)日:2022-04-28

    申请号:US17389841

    申请日:2021-07-30

    Abstract: A semiconductor memory device includes a first substrate including opposite first and second surfaces, a mold structure including gate electrodes stacked on the first surface of the first substrate, a channel structure through the mold structure, a first contact via penetrating the first substrate, a second substrate including opposite third and fourth surfaces, a circuit element on the third surface of the second substrate, a first through-via through the mold structure connecting the first contact via and the circuit element, the first through-via including a first conductive pattern, and a first spacer separating the first conductive pattern from the mold structure, and a second through-via through the mold structure and spaced apart from the first through-via, the second through-via including a second conductive pattern, and a second spacer separating the second conductive pattern from the first substrate and the mold structure.

    SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20250151272A1

    公开(公告)日:2025-05-08

    申请号:US18746736

    申请日:2024-06-18

    Abstract: Semiconductor memory devices including memory cells arranged three-dimensionally, methods for fabricating the same, and electronic systems including the same are provided. The semiconductor memory device includes a first stacked structure including first gate electrodes sequentially stacked and spaced apart from each other, a second stacked structure on the first stacked structure and including second gate electrodes sequentially stacked and spaced apart from each other, and a channel structure extending in a vertical direction and passing through the first and second stacked structures, wherein the channel structure includes a channel layer including a first pillar portion crossing the first gate electrodes, a second pillar portion crossing the second gate electrodes, and a horizontal portion extending along a plane crossing the vertical direction, the horizontal portion connecting the first and second pillar portions, and a data storage layer extending along an outer side of the channel layer.

    SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20240064974A1

    公开(公告)日:2024-02-22

    申请号:US18386639

    申请日:2023-11-03

    CPC classification number: H10B41/27 H01L23/5384 H01L25/0657 H10B43/27

    Abstract: A semiconductor memory device comprising: a first semiconductor chip including an upper input/output pad, a second semiconductor chip including a lower input/output pad, and a substrate attachment film attaching the first and second semiconductor chips. The first and second semiconductor chips each include a first substrate including a first side facing the substrate attachment film and a second side, a mold structure including gate electrodes, a channel structure penetrating the mold structure and intersecting the gate electrodes, a second substrate including a third side facing the first side and a fourth side, a first circuit element on the third side of the second substrate, and a contact via penetrating the first substrate and connected to the first circuit element. The upper and lower input/output pads are on the second sides of the first and second semiconductor chip, respectively, and contact the contact vias of the first and second semiconductor chips.

    SEMICONDUCTOR MEMORY DEVICE, METHOD FOR FABRICATING THE SAME AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20230114139A1

    公开(公告)日:2023-04-13

    申请号:US17900172

    申请日:2022-08-31

    Abstract: A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

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