公开(公告)号：US20210265334A1

公开(公告)日：2021-08-26

申请号：US16853535

申请日：2020-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Traynor ,  Tanya Abaya ,  Dharmendar Palle ,  Mark S. Rodder

IPC: H01L27/02 ,  H01L23/528 ,  G06F30/392

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

公开(公告)号：US10971420B2

公开(公告)日：2021-04-06

申请号：US16374524

申请日：2019-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Vassilios Gerousis

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/522 ,  H01L25/065 ,  H01L27/06

Abstract: A monolithic three-dimensional integrated circuit including a first device, a second device on the first device, and a thermal shield stack between the first device and the second device. The thermal shield stack includes a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction. The thermal shield stack of the monolithic three-dimensional integrated circuit includes only dielectric materials.

公开(公告)号：US20200373241A1

公开(公告)日：2020-11-26

申请号：US16561340

申请日：2019-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Michael Traynor

IPC: H01L23/528 ,  H01L23/522

Abstract: A tap cell configured to enable electrical connection from a buried power rail of an integrated circuit to a power distribution network includes. The tap cell includes a buried power rail layer including VDD and VSS power supply lines, insulating layers and metal layers alternately arranged on the buried power rail layer, a first power supply interconnect in metal layer M1 or higher electrically coupled to the VDD power supply line, and a second power supply interconnect in metal layer M1 or higher electrically connected to the VSS power supply line. The first power supply interconnect and the second power supply interconnect are configured to be electrically connected to the power distribution network, and the VDD and VSS power supply lines are configured to supply power from the power distribution network to the buried power rail of the integrated circuit. The tap cell is free of any active semiconductor devices.

公开(公告)号：US20200135735A1

公开(公告)日：2020-04-30

申请号：US16298887

申请日：2019-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Joon Goo Hong ,  Vassilios Gerousis ,  Mark S. Rodder

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.