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    Power distribution network using buried power rail
    1.
    发明授权
    Power distribution network using buried power rail 有权

    公开(公告)号：US10886224B2

    公开(公告)日：2021-01-05

    申请号：US16561340

    申请日：2019-09-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Michael Traynor

    IPC: H01L23/528 ,  H01L23/522

    Abstract: A tap cell configured to enable electrical connection from a buried power rail of an integrated circuit to a power distribution network includes. The tap cell includes a buried power rail layer including VDD and VSS power supply lines, insulating layers and metal layers alternately arranged on the buried power rail layer, a first power supply interconnect in metal layer M1 or higher electrically coupled to the VDD power supply line, and a second power supply interconnect in metal layer M1 or higher electrically connected to the VSS power supply line. The first power supply interconnect and the second power supply interconnect are configured to be electrically connected to the power distribution network, and the VDD and VSS power supply lines are configured to supply power from the power distribution network to the buried power rail of the integrated circuit. The tap cell is free of any active semiconductor devices.

    METHOD OF FORMING SACRIFICIAL SELF-ALIGNED FEATURES FOR ASSISTING DIE-TO-DIE AND DIE-TO-WAFER DIRECT BONDING
    4.
    发明申请
    METHOD OF FORMING SACRIFICIAL SELF-ALIGNED FEATURES FOR ASSISTING DIE-TO-DIE AND DIE-TO-WAFER DIRECT BONDING 有权

    公开(公告)号：US20210183814A1

    公开(公告)日：2021-06-17

    申请号：US16861029

    申请日：2020-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wei-E Wang ,  Mark S. Rodder ,  Vassilios Gerousis

    IPC: H01L25/065 ,  H01L23/00

    Abstract: A method of manufacturing a three-dimensional semiconductor device includes forming a bi-layer sacrificial stack on a top wafer and a bottom wafer each including a series of interconnects in a dielectric substrate. The bi-layer sacrificial stack includes a second sacrificial layer on a first sacrificial layer. The method also includes selectively etching the second sacrificial layers to form a first pattern of projections on the top wafer and a second pattern of projections on the bottom wafer. The first pattern of projections is configured to mesh with the second pattern of projections. The method also includes positioning the top wafer on the bottom wafer and releasing the top wafer such that engagement between the first pattern of projections and the second pattern of projections self-aligns the plurality of interconnects of the top wafer with the plurality of interconnects of the bottom wafer within a misalignment error.

    Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding
    6.
    发明授权
    Method of forming sacrificial self-aligned features for assisting die-to-die and die-to-wafer direct bonding 有权

    公开(公告)号：US11189600B2

    公开(公告)日：2021-11-30

    申请号：US16861029

    申请日：2020-04-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Wei-E Wang ,  Mark S. Rodder ,  Vassilios Gerousis

    IPC: H01L25/065 ,  H01L23/532 ,  H01L23/00

    Abstract: A method of manufacturing a three-dimensional semiconductor device includes forming a bi-layer sacrificial stack on a top wafer and a bottom wafer each including a series of interconnects in a dielectric substrate. The bi-layer sacrificial stack includes a second sacrificial layer on a first sacrificial layer. The method also includes selectively etching the second sacrificial layers to form a first pattern of projections on the top wafer and a second pattern of projections on the bottom wafer. The first pattern of projections is configured to mesh with the second pattern of projections. The method also includes positioning the top wafer on the bottom wafer and releasing the top wafer such that engagement between the first pattern of projections and the second pattern of projections self-aligns the plurality of interconnects of the top wafer with the plurality of interconnects of the bottom wafer within a misalignment error.

    Semiconductor device and method for making the same
    10.
    发明授权
    Semiconductor device and method for making the same 有权

    公开(公告)号：US10811415B2

    公开(公告)日：2020-10-20

    申请号：US16298887

    申请日：2019-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Rwik Sengupta ,  Joon Goo Hong ,  Vassilios Gerousis ,  Mark S. Rodder

    IPC: H01L27/092 ,  H01L23/528 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78

    Abstract: According to some example embodiments of the present disclosure, a semiconductor device includes: a substrate; a first semiconductor layer over the substrate, the first semiconductor layer being a first type of semiconductor device; and a second semiconductor layer over the substrate and the first semiconductor layer, the second semiconductor layer being the first type of semiconductor device, wherein a first portion of the first semiconductor layer overlaps the second semiconductor layer when viewed in a direction perpendicular to a plane of the substrate and a second portion of the first semiconductor layer is laterally offset from the second semiconductor layer when viewed in the direction perpendicular to the plane of the substrate.

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