DECODER, IMAGE PROCESSING DEVICE, AND OPERATING METHOD OF THE IMAGE PROCESSING DEVICE

    公开(公告)号:US20240212214A1

    公开(公告)日:2024-06-27

    申请号:US18392713

    申请日:2023-12-21

    CPC classification number: G06T9/00

    Abstract: An image processing device includes an interface configured to receive compressed data obtained by compressing image data corresponding to an output of at least one pixel and a decoder configured to generate at least two different pieces of compensation data based on loss data included in the compressed data and generate decompressed data by decompressing the compressed data based on any one piece of compensation data among the at least two different pieces of compensation data, where the loss data corresponds to data lost due to compression of the image data.

    METHOD AND ELECTRONIC APPARATUS WITH PARALLEL SINGLE-STAGE SWITCHING

    公开(公告)号:US20240205169A1

    公开(公告)日:2024-06-20

    申请号:US18354341

    申请日:2023-07-18

    CPC classification number: H04L49/15

    Abstract: An electronic apparatus includes a plurality of processor device-memory device groups, and each of the plurality of processor device-memory device groups includes a plurality of memory devices respectively comprising one or more memories, a plurality of processor devices respectively comprising one or more processors, and a plurality of switches. Each of the plurality of switches includes a plurality of ports. Each of first memory devices included in a first processor device-memory device group of the plurality of processor device-memory device groups is connected to a first subset of ports of one switch of first switches included in the first processor device-memory device group, and to a first subset of ports of one switch of second switches of the plurality of switches included in a second processor device-memory device group of the plurality of processor device-memory device groups.

    MESSAGE SPLIT-AGGREGATION FOR MULTI-STAGE ELECTRICAL INTERCONNECTION NETWORK

    公开(公告)号:US20230254253A1

    公开(公告)日:2023-08-10

    申请号:US18101732

    申请日:2023-01-26

    CPC classification number: H04L47/18 G06F13/4068

    Abstract: Message splitting and aggregation in a multi-stage electrical interconnection network are disclosed. A method of operating an electronic device comprised of computing devices, includes splitting, into segments, a message to be transmitted from a first of the computing devices, transmitting the segments to a second of the computing devices through a multi-channel that is based on an electrical connection between the first computing device and a plurality of switches, wherein the multi-channel includes channels respectively including electrical connections, the electrical connections connecting the first computing device with the second computing device, and reconstructing the message by aggregating the segments in the second computing device, wherein a bandwidth of the multi-channel transmitting the segments is greater than a maximum bandwidth of a single electrical connection of the electrical connections.

    CAMERA MODULE, IMAGE PROCESSING DEVICE AND IMAGE COMPRESSION METHOD

    公开(公告)号:US20230164362A1

    公开(公告)日:2023-05-25

    申请号:US18150046

    申请日:2023-01-04

    CPC classification number: H04N19/85 H04N19/42 H04N19/182 H04N19/184 H04N19/186

    Abstract: A camera module includes a compressor configured to divide a plurality of pixels included in image data, into a plurality of pixel groups, with respect to each of the plurality of pixel groups into which the plurality of pixels is divided, calculate a representative pixel value of a corresponding pixel group, based on pixel values of multiple pixels included in the corresponding pixel group, generate first compressed data, based on the calculated representative pixel value of each of the plurality of pixel groups, with respect to each of the plurality of pixel groups into which the plurality of pixels is divided, calculate residual values representing differences between the pixel values of the multiple pixels included in the corresponding pixel group and the representative pixel value of the corresponding pixel group, and generate second compressed data, based on the calculated residual values of each of the plurality of pixel groups.

    IMAGE SENSOR INCLUDING A TRANSISTOR WITH A VERTICAL CHANNEL AND A METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20220384512A1

    公开(公告)日:2022-12-01

    申请号:US17743788

    申请日:2022-05-13

    Abstract: An image sensor includes: photodiodes arranged in a substrate; active pillars connected to the photodiodes and extending in a vertical direction perpendicular to a bottom surface of the substrate; at least two transistors stacked in the vertical direction, wherein portions of the active pillars are channel areas of the at least two transistors; a floating diffusion (FD) area disposed under a transfer transistor, which is one of the at least two transistors, wherein the FD area is configured to receive charge from the photodiode through the transfer transistor and the portions of the active pillars; and a light transmitting layer disposed on a top surface of the substrate.

    APPARATUS FOR ENCODING IMAGE, APPARATUS FOR DECODING IMAGE AND IMAGE SENSOR

    公开(公告)号:US20220217293A1

    公开(公告)日:2022-07-07

    申请号:US17705784

    申请日:2022-03-28

    Inventor: Wonseok LEE

    Abstract: An image encoding apparatus includes a compressor that generates a bitstream including encoded data corresponding to values of original pixels, based on one of encoding modes, and a reconstructor that generates values of reference pixels by reconstructing the bitstream. In a first mode of the encoding modes, the compressor generates the bitstream based on a difference value between each of the values of the original pixels and a reference value which is based on at least one of the values of the reference pixels. In a second mode of the encoding modes, the compressor generates the bitstream based on an average value of at least two of the values of the original pixels.

    METHOD AND DEVICE WITH NETWORK TOPOLOGY FORMATION

    公开(公告)号:US20240179086A1

    公开(公告)日:2024-05-30

    申请号:US18308872

    申请日:2023-04-28

    CPC classification number: H04L45/02

    Abstract: A device includes: a processor configured to execute instructions in a memory, wherein, the instructions are configured to cause the processor to: select a first network group from among network groups, wherein the first network group is selected from among the network groups based on numbers of global links connecting the network groups, respectively; obtain a first list of network groups, among the network groups, that are not connected to the first network group; select a second network group and a third network group from among the network groups in the first list based on connections between the network groups in the first list; and based on the selecting of the first, second, and third network groups, form a topology including global links connecting the first network group, the second network group, and the third network group each to each other.

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