公开(公告)号：US20240006356A1

公开(公告)日：2024-01-04

申请号：US18181731

申请日：2023-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： INHYO HWANG ,  YOUNG LYONG KIM ,  HYUNSOO CHUNG

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/58 ,  H10B80/00 ,  H01L21/78

CPC classification number: H01L24/06 ,  H01L22/32 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/08 ,  H01L2924/35121 ,  H01L21/78 ,  H01L22/12 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B80/00

Abstract: A semiconductor device may include a first substrate including device and edge regions, a first insulating structure on the first substrate, first metal pads and first dummy pads at the uppermost end of the first insulating structure, a second insulating structure on the first insulating structure, second metal pads and second dummy pads at the lowermost end of the second insulating structure, a first interconnection structure in the first insulating structure, electrically connected to the first metal pads and electrically isolated from the first dummy pads, and a second interconnection structure in the second insulating structure, electrically connected to the second metal pads, and electrically isolated from the second dummy pads. Ones of the first metal pads may be in contact with respective ones of the second metal pads on the device region, and ones of the first dummy pads may be in contact with respective ones of the second dummy pads on the edge region.

公开(公告)号：US20220352124A1

公开(公告)日：2022-11-03

申请号：US17535904

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG LYONG KIM

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip mounted on a substrate, a first conductive post disposed on the substrate and spaced apart from the first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and the first conductive post, and a mold layer on the substrate that covers the first and second semiconductor chips and the first conductive post. The second semiconductor chip is supported on the first semiconductor chip by a first dummy solder terminal provided between the first and second semiconductor chips, and is coupled to the first conductive post by a first signal solder terminal provided between the first conductive post and the second semiconductor chip. The first dummy solder terminal is in direct contact with a top surface of the first semiconductor chip, and is electrically disconnected from the second semiconductor chip.

公开(公告)号：US20220149013A1

公开(公告)日：2022-05-12

申请号：US17582079

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： AE-NEE JANG ,  YOUNG LYONG KIM

IPC: H01L25/065 ,  H01L23/31

Abstract: Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.