公开(公告)号：US20250096215A1

公开(公告)日：2025-03-20

申请号：US18626787

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  CHI WOO LEE

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498

Abstract: A semiconductor package includes a redistribution structure, a semiconductor die on the redistribution structure, one or more memory stacking structures disposed on the redistribution structure, wherein the one or more memory stacking structures and the semiconductor die are arranged side by side on the redistribution structure, an optical engine disposed on the redistribution structure, wherein the optical engine and the semiconductor die are arranged side by side on the redistribution structure, and a heat dissipation structure on the semiconductor die, the one or more memory stacking structures, and the optical engine, wherein levels of upper surfaces of the semiconductor die, the one or more memory stacking structures, and the optical engine are the same.

公开(公告)号：US20250054913A1

公开(公告)日：2025-02-13

申请号：US18581483

申请日：2024-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  WON-YOUNG KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device includes first to third semiconductor chips consecutively stacked. The first semiconductor chip comprises a first semiconductor substrate. A circuit layer is on a top surface of the first semiconductor substrate. First pads are on a top surface of the circuit layer. The first pads are electrically connected to the circuit layer. The second semiconductor chip comprises a second semiconductor substrate. Passive devices are in the second semiconductor substrate. Second pads are on a bottom surface of the second semiconductor substrate. The second pads are electrically connected to the passive devices. Third pads are on a top surface of the second semiconductor substrate. The third semiconductor chip comprises fourth pads on a bottom surface of the third semiconductor chip. The first pads and the second pads are directly connected to each other. The third pads and the fourth pads are directly connected to each other.

公开(公告)号：US20220415809A1

公开(公告)日：2022-12-29

申请号：US17539963

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG LYONG KIM ,  HYUNSOO CHUNG ,  INHYO HWANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.

公开(公告)号：US20250087570A1

公开(公告)日：2025-03-13

申请号：US18626700

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  CHI WOO LEE

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution layer structure, a first sub-package positioned on the redistribution layer structure, a second sub-package positioned on the first sub-package, and a first encapsulant positioned on the first sub-package and encapsulating the second sub-package. The first sub-package includes a first semiconductor chip including a first chip through via and a dielectric through via electrically connected to the redistribution layer structure. The second sub-package includes a second semiconductor chip including a plurality of second chip through vias, each second chip through via electrically connected to one of the first chip through via and the dielectric through via, a third semiconductor chip positioned on the second semiconductor chip, and a fourth semiconductor chip positioned on the third semiconductor chip. Each of the second to fourth semiconductor chips is exposed at a side surface of the second sub-package and covered with the first encapsulant.

公开(公告)号：US20240040805A1

公开(公告)日：2024-02-01

申请号：US18122285

申请日：2023-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNSOO CHUNG ,  YOUNG LYONG KIM ,  Inhyo HWANG

IPC: H10B80/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC classification number: H10B80/00 ,  H01L25/50 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package may include a substrate, a chip structure mounted on the substrate, and a first dummy structure attached to the chip structure. The chip structure may include a first semiconductor chip, a second dummy structure disposed at a side of the first semiconductor chip, and a mold layer enclosing the first semiconductor chip and the second dummy structure. A bottom surface of the first semiconductor chip, a bottom surface of the second dummy structure, and a bottom surface of the mold layer may be coplanar with each other.

公开(公告)号：US20230023883A1

公开(公告)日：2023-01-26

申请号：US17568361

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  YOUNG LYONG KIM ,  INHYO HWANG

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a buried solder ball on the substrate and spaced apart from the first semiconductor chip, a first molding layer on the substrate and encapsulating and exposing the first semiconductor chip and the buried solder ball, a second semiconductor chip on the first molding layer and vertically overlapping the buried solder ball and a portion of the first semiconductor chip, and a second molding layer on the first molding layer and covering the second semiconductor chip. The second semiconductor chip is supported on the first semiconductor chip through a dummy solder ball between the first and second semiconductor chips. The second semiconductor chip is connected to the buried solder ball through a signal solder ball between the buried solder ball and the second semiconductor chip.

公开(公告)号：US20230005814A1

公开(公告)日：2023-01-05

申请号：US17705931

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  YOUNGLYONG KIM ,  INHYO HWANG

IPC: H01L23/427 ,  H01L23/498

Abstract: A semiconductor package includes an interposer, a first semiconductor chip attached onto the interposer, second semiconductor chips stacked on the first semiconductor chip, at least two heat sinks mounted on the interposer and spaced apart from the second semiconductor chips, and a molding layer surrounding the second semiconductor chips and the at least two heat sinks.

公开(公告)号：US20170103958A1

公开(公告)日：2017-04-13

申请号：US15213505

申请日：2016-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANHO LEE ,  MYEONG SOON PARK ,  HYUNSOO CHUNG

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L23/562 ,  H01L24/06 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0903 ,  H01L2224/09154 ,  H01L2224/1403 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/1712 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A semiconductor package includes a semiconductor chip mounted on a substrate that has a top surface and a bottom surface opposite to each other, and connection members that connect the substrate and the semiconductor chip to each other. The connection members include first connection members disposed on a central region of the semiconductor chip and that have heights equal to each other, and second connection members disposed on an edge region of the semiconductor chip and that have heights equal to each other. The heights of the first connection members differ from the heights of the second connection members.

公开(公告)号：US20250046757A1

公开(公告)日：2025-02-06

申请号：US18589650

申请日：2024-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  JAESIC LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H10B80/00

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a base die that includes first dummy pads on an edge at a top surface of the base die; a plurality of memory dies on the base die; a plurality of conductive posts spaced apart from the memory dies and on the edge of the base die; a mold layer that covers the base die, the memory dies, and the conductive posts; and a heat spreader that includes second dummy pads on an edge at a bottom surface of the heat spreader and third dummy pads on a central portion of the bottom surface of the heat spreader, wherein the heat spreader is disposed on the memory dies and the mold layer. The first dummy pads are correspondingly connected to the second dummy pads through the conductive posts and the second dummy pads are in contact with the conductive posts.

公开(公告)号：US20250015048A1

公开(公告)日：2025-01-09

申请号：US18405107

申请日：2024-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  SANG CHEON PARK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H10B80/00

Abstract: A semiconductor stack structure includes: a plurality of semiconductor dies vertically stacked on each other; and one or more dummy dies positioned between the plurality of semiconductor dies, wherein each of the one or more dummy dies includes: a dummy die base; a first interconnection structure positioned on a first side of the dummy die base and including a plurality of first bonding pads, wherein the first bonding pads are positioned at substantially regular intervals; and a second interconnection structure positioned on a second side of the dummy die base and including a plurality of second bonding pads, wherein the second bonding pads are positioned at substantially regular intervals.