公开(公告)号：US11145757B2

公开(公告)日：2021-10-12

申请号：US16713054

申请日：2019-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Chai Jung ,  Seon Bae Kim ,  Seung Hyun Song

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/085

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.

公开(公告)号：US20210111271A1

公开(公告)日：2021-04-15

申请号：US16824196

申请日：2020-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Bae Kim ,  Seung Hyun Song ,  Young Chai Jung

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/06

Abstract: A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure.