公开(公告)号：US11309405B2

公开(公告)日：2022-04-19

申请号：US16846813

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi Chan Jun ,  Min Gyu Kim ,  Seon Bae Kim

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8234

Abstract: A method for manufacturing a vertical field effect transistor (VFET) device may include: providing an intermediate VFET structure including a substrate, a plurality of fin structures formed thereon, and a doped layer formed on the substrate between the fin structures, the doped layer comprising a bottom source/drain (S/D) region; forming a shallow trench through the doped layer and the substrate below a top surface of the substrate and between the fin structures, to isolate the fin structures from each other; filling the shallow trench and a space between the fin structures with an insulating material; etching the insulating material filled between the fin structures above a level of a top surface of the doped layer, except in the shallow trench, such that a shallow trench isolation (STI) structure having a top surface to be at or above a level of the top surface of the doped layer is formed in the shallow trench; forming a plurality of gate structures on the fin structures, respectively; and forming a top S/D region above the fin structures.

公开(公告)号：US11837548B2

公开(公告)日：2023-12-05

申请号：US17476985

申请日：2021-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon Bae Kim ,  Seo Woo Nam

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L21/3213 ,  H01L23/528

CPC classification number: H01L23/53295 ,  H01L21/3213 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283

Abstract: A semiconductor device includes a substrate, a first interlayer insulating layer disposed on the substrate, a first trench formed inside the first interlayer insulating layer, a contact plug disposed inside the first trench, a first wiring pattern disposed on the contact plug, a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction, a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern, and a first air gap formed on the contact plug inside the first trench.

公开(公告)号：US11271091B2

公开(公告)日：2022-03-08

申请号：US16775550

申请日：2020-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seon Bae Kim ,  Seung Hyun Song ,  Ki Il Kim ,  Young Chai Jung

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/78

Abstract: A method for manufacturing a fin structure for a vertical field effect transistor (VFET) includes: forming on a substrate mandrels having at least one first gap therebetween; forming first spacers on side surfaces of the mandrels such that at least one second gap, smaller than the first gap, is formed between the first spacers; forming a second spacer on side surfaces of the first spacers; removing the mandrels and the first spacers to leave the second spacer on the side surfaces of the first spacers; removing the second spacer, on the side surfaces of the first spacers, at a predetermined portion so that the remaining second spacer has a same two-dimensional (2D) shape as the fin structure; and removing a portion of the substrate, except below the remaining second spacer, and the remaining second spacer so that the substrate below the remaining second spacer forms the fin structure.

公开(公告)号：US11145757B2

公开(公告)日：2021-10-12

申请号：US16713054

申请日：2019-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Chai Jung ,  Seon Bae Kim ,  Seung Hyun Song

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/085

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.

公开(公告)号：US11735659B2

公开(公告)日：2023-08-22

申请号：US17474217

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Chai Jung ,  Seon Bae Kim ,  Seung Hyun Song

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/085 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L27/085 ,  H01L29/41791 ,  H01L29/66666

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.

公开(公告)号：US10790368B2

公开(公告)日：2020-09-29

申请号：US16275675

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Chai Jung ,  Myung Gil Kang ,  Kang Ill Seo ,  Seon Bae Kim ,  Yong Hee Park

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L23/522

Abstract: VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.