中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

26 records (took 0.027 seconds)

    Symmetrical two-dimensional fin structure for vertical field effect transistor and method for manufacturing the same
    2.
    发明授权
    Symmetrical two-dimensional fin structure for vertical field effect transistor and method for manufacturing the same 有权

    公开(公告)号：US11296210B2

    公开(公告)日：2022-04-05

    申请号：US16824196

    申请日：2020-03-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seon-Bae Kim ,  Seung Hyun Song ,  Young Chai Jung

    IPC: H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L21/033

    Abstract: A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure.

    Integrated circuit devices including a vertical field-effect transistor (VFET) and a fin field-effect transistor (FinFET) and methods of forming the same
    3.
    发明授权
    Integrated circuit devices including a vertical field-effect transistor (VFET) and a fin field-effect transistor (FinFET) and methods of forming the same 有权

    公开(公告)号：US10910370B2

    公开(公告)日：2021-02-02

    申请号：US16358245

    申请日：2019-03-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Hyun Song ,  Young Chai Jung

    IPC: H01L27/088 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234

    Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a channel region protruding from a substrate in a vertical direction, a first source/drain region, and a second source/drain region. The first source/drain region may vertically overlap the channel region. The first and second source/drain regions may contact a first portion and a second portion of the channel region, respectively, and a third portion of the channel region between the first and second portions may include a first channel region extending longitudinally in a first horizontal direction that is perpendicular to the vertical direction and a second channel region extending longitudinally in a second horizontal direction that is perpendicular to the vertical direction and traverses the first horizontal direction. The integrated circuit devices may also include a gate structure on opposing vertical sides of the channel region.

    INTEGRATED CIRCUIT DEVICES INCLUDING TRANSISTORS HAVING VARIABLE CHANNEL PITCHES
    4.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING TRANSISTORS HAVING VARIABLE CHANNEL PITCHES 审中-公开

    公开(公告)号：US20200295146A1

    公开(公告)日：2020-09-17

    申请号：US16520717

    申请日：2019-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JUNG HO DO ,  Seung Hyun Song

    IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L27/02

    Abstract: Integrated circuit devices may include active regions spaced apart from each other in a direction. The active regions may include a first pair of active regions, a second pair of active regions, and a third pair of active regions. The first pair of active regions may be spaced apart from each other by a first distance in the direction, the second pair of active regions may be spaced apart from each other by the first distance in the direction, and the third pair of active regions may be spaced apart from each other by the first distance in the direction. The second pair of active regions may be spaced apart from the first pair of active regions and the third pair of active regions by a second distance in the direction, and the first distance may be shorter than the second distance.

    INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) AND METHODS OF FORMING THE SAME
    7.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210376126A1

    公开(公告)日：2021-12-02

    申请号：US17399118

    申请日：2021-08-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

    IPC: H01L29/66

    Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

Patent Agency Ranking