公开(公告)号：US11107906B2

公开(公告)日：2021-08-31

申请号：US16798482

申请日：2020-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

IPC: H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

公开(公告)号：US11296210B2

公开(公告)日：2022-04-05

申请号：US16824196

申请日：2020-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seon-Bae Kim ,  Seung Hyun Song ,  Young Chai Jung

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L21/033

Abstract: A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure.

公开(公告)号：US10910370B2

公开(公告)日：2021-02-02

申请号：US16358245

申请日：2019-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun Song ,  Young Chai Jung

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a channel region protruding from a substrate in a vertical direction, a first source/drain region, and a second source/drain region. The first source/drain region may vertically overlap the channel region. The first and second source/drain regions may contact a first portion and a second portion of the channel region, respectively, and a third portion of the channel region between the first and second portions may include a first channel region extending longitudinally in a first horizontal direction that is perpendicular to the vertical direction and a second channel region extending longitudinally in a second horizontal direction that is perpendicular to the vertical direction and traverses the first horizontal direction. The integrated circuit devices may also include a gate structure on opposing vertical sides of the channel region.

公开(公告)号：US11699754B2

公开(公告)日：2023-07-11

申请号：US17563608

申请日：2021-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun Song ,  Chang Woo Sohn ,  Young Chai Jung ,  Sa Hwan Hong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666

Abstract: A vertical field-effect transistor (VFET) includes: a fin structure on a substrate; a gate structure including a gate dielectric layer on an upper portion of a sidewall of the fin structure, and a conductor layer on a lower portion of the gate dielectric layer; a top source/drain (S/D) region above the fin structure and the gate structure; a bottom S/D region below the fin structure and the gate structure; a top spacer on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.

公开(公告)号：US20210376126A1

公开(公告)日：2021-12-02

申请号：US17399118

申请日：2021-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

IPC: H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

公开(公告)号：US11735659B2

公开(公告)日：2023-08-22

申请号：US17474217

申请日：2021-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Chai Jung ,  Seon Bae Kim ,  Seung Hyun Song

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/085 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L27/085 ,  H01L29/41791 ,  H01L29/66666

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.

公开(公告)号：US11552182B2

公开(公告)日：2023-01-10

申请号：US17399118

申请日：2021-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

IPC: H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

公开(公告)号：US10790368B2

公开(公告)日：2020-09-29

申请号：US16275675

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Chai Jung ,  Myung Gil Kang ,  Kang Ill Seo ,  Seon Bae Kim ,  Yong Hee Park

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L23/522

Abstract: VFET devices are provided. A VFET device includes a substrate including first and second protruding portions. The VFET device includes an isolation region between the first and second protruding portions. The VFET device includes first and second silicide regions on the first and second protruding portions, respectively. Moreover, the VFET device includes a contact on the first and second silicide regions. Related methods of forming a VFET device are also provided.

公开(公告)号：US11271091B2

公开(公告)日：2022-03-08

申请号：US16775550

申请日：2020-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seon Bae Kim ,  Seung Hyun Song ,  Ki Il Kim ,  Young Chai Jung

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/78

Abstract: A method for manufacturing a fin structure for a vertical field effect transistor (VFET) includes: forming on a substrate mandrels having at least one first gap therebetween; forming first spacers on side surfaces of the mandrels such that at least one second gap, smaller than the first gap, is formed between the first spacers; forming a second spacer on side surfaces of the first spacers; removing the mandrels and the first spacers to leave the second spacer on the side surfaces of the first spacers; removing the second spacer, on the side surfaces of the first spacers, at a predetermined portion so that the remaining second spacer has a same two-dimensional (2D) shape as the fin structure; and removing a portion of the substrate, except below the remaining second spacer, and the remaining second spacer so that the substrate below the remaining second spacer forms the fin structure.

公开(公告)号：US11233146B2

公开(公告)日：2022-01-25

申请号：US16828049

申请日：2020-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun Song ,  Chang Woo Sohn ,  Young Chai Jung ,  Sa Hwan Hong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/40

Abstract: A vertical field-effect transistor (VFET) device and a method of manufacturing the same are provided. The VFET device includes: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure, and a conductor layer formed on a lower portion of the gate dielectric layer; a top source/drain (S/D) region formed above the fin structure and the gate structure; a bottom S/D region formed below the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.