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公开(公告)号：US11798631B2
公开(公告)日：2023-10-24
申请号：US17507606
申请日：2021-10-21
发明人： Iris Lu , Tai-Yuan Tseng
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/26
摘要： Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.
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