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1.发明公开公开(公告)号：US20230207022A1
公开(公告)日：2023-06-29
申请号：US17562123
申请日：2021-12-27
发明人： Iris Lu , Tai-Yuan Tseng , Chia-Kai Chou
CPC分类号： G11C16/26 , G11C16/24 , G11C16/3459 , G11C16/0483 , G11C11/1673 , G11C11/1655 , G11C11/1657 , G11C11/1677 , H01L25/0657
摘要： A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.
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公开(公告)号：US11301176B2
公开(公告)日：2022-04-12
申请号：US16909484
申请日：2020-06-23
发明人： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
IPC分类号： G06F3/06 , G06F9/30 , G06F9/38 , G11C11/00 , G11C5/06 , G11C11/4072 , G06F8/65 , G11C29/16 , G11C5/14 , G11C16/28 , G11C11/56 , G11C29/46 , G11C16/34 , G11C16/24 , G11C16/10 , G11C16/08
摘要： A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.
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公开(公告)号：US20190179568A1
公开(公告)日：2019-06-13
申请号：US16015624
申请日：2018-06-22
发明人： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
摘要： An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.
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公开(公告)号：US20180366178A1
公开(公告)日：2018-12-20
申请号：US15627947
申请日：2017-06-20
发明人： Anirudh Amarnath , Tai-Yuan Tseng
IPC分类号： G11C11/4091 , G11C11/4094
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/062 , G11C7/08 , G11C7/12 , G11C11/24 , G11C11/4094 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/32 , G11C2211/5642
摘要： A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. A voltage supply circuit may supply a selected pulse and an unselected pulse to the selected and unselected sense circuits. The selected sense circuits may pass the selected pulse to associated charge-storing circuits, and reject the unselected pulse. The unselected sense circuits may pass the unselected pulse to associated charge-storing circuits, and reject the selected pulse. In addition, voltage-setting circuitry may set sense voltages in the unselected sense circuits to a pre-sense level that matches the pre-sense level of communication voltages in the unselected sense circuits.
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公开(公告)号：US11978516B2
公开(公告)日：2024-05-07
申请号：US17718124
申请日：2022-04-11
发明人： Yanjie Wang , Ohwon Kwon , Kou Tei , Tai-Yuan Tseng , Yasue Yamamoto , Yonggang Wu , Guirong Liang
IPC分类号： G11C16/04 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/34 , H01L23/00 , H01L25/065
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/30 , G11C16/3459 , H01L24/08 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L2224/08148 , H01L2224/16225 , H01L2224/48149 , H01L2224/48229 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06562
摘要： A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.
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公开(公告)号：US11915769B2
公开(公告)日：2024-02-27
申请号：US17745120
申请日：2022-05-16
发明人： Kei Kitamura , Iris Lu , Tai-Yuan Tseng
CPC分类号： G11C16/3459 , G11C7/1039 , G11C7/1048 , G11C16/102 , G11C16/24 , G11C16/26
摘要： A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.
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公开(公告)号：US20230130365A1
公开(公告)日：2023-04-27
申请号：US17507606
申请日：2021-10-21
发明人： Iris Lu , Tai-Yuan Tseng
摘要： Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.
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公开(公告)号：US10510383B2
公开(公告)日：2019-12-17
申请号：US15723422
申请日：2017-10-03
发明人： Tai-Yuan Tseng , Anirudh Amarnath
IPC分类号： G11C7/00 , G11C7/12 , G11C16/24 , G11C29/12 , G11C16/34 , G11C16/26 , G11C11/56 , G11C16/08 , G11C16/04
摘要： A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. The selected and unselected sense circuits are configured to perform a state-dependent pre-charge operation during the sense operation. In particular, the selected sense circuits may enable respective pre-charge circuit paths that supply a pre-charge supply voltage to respective sense nodes in the selected sense circuits. Additionally, the unselected sense circuits may disable respective pre-charge circuit paths to prevent the supply of the pre-charge supply voltage to respective sense nodes in the unselected sense circuits. A sense circuit controller may control latches to control the enabling and disabling of the pre-charge circuit paths.
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公开(公告)号：US20190088335A1
公开(公告)日：2019-03-21
申请号：US15942044
申请日：2018-03-30
发明人： Chia-Lin Hsiung , Fumiaki Toyama , Tai-Yuan Tseng , Yan Li
IPC分类号： G11C16/08 , H01L27/11556 , H01L23/528 , H01L27/11582 , G11C16/04
摘要： A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.
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公开(公告)号：US11929125B2
公开(公告)日：2024-03-12
申请号：US17355615
申请日：2021-06-23
发明人： Tai-Yuan Tseng , Chia-Kai Chou , Iris Lu
CPC分类号： G11C16/3459 , G11C7/065 , G11C16/102 , G11C16/24 , G11C16/26
摘要： Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.
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