MICROCONTROLLER INSTRUCTION MEMORY ARCHITECTURE FOR NON-VOLATILE MEMORY

    公开(公告)号:US20190179568A1

    公开(公告)日:2019-06-13

    申请号:US16015624

    申请日:2018-06-22

    IPC分类号: G06F3/06 G06F9/32

    摘要: An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.

    Non-volatile memory with isolation latch shared between data latch groups

    公开(公告)号:US11915769B2

    公开(公告)日:2024-02-27

    申请号:US17745120

    申请日:2022-05-16

    摘要: A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.

    TRANSFER LATCH TIERS
    7.
    发明申请

    公开(公告)号:US20230130365A1

    公开(公告)日:2023-04-27

    申请号:US17507606

    申请日:2021-10-21

    IPC分类号: G11C16/24 G11C16/04 G11C16/26

    摘要: Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.

    State dependent sense circuits and pre-charge operations for storage devices

    公开(公告)号:US10510383B2

    公开(公告)日:2019-12-17

    申请号:US15723422

    申请日:2017-10-03

    摘要: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. The selected and unselected sense circuits are configured to perform a state-dependent pre-charge operation during the sense operation. In particular, the selected sense circuits may enable respective pre-charge circuit paths that supply a pre-charge supply voltage to respective sense nodes in the selected sense circuits. Additionally, the unselected sense circuits may disable respective pre-charge circuit paths to prevent the supply of the pre-charge supply voltage to respective sense nodes in the unselected sense circuits. A sense circuit controller may control latches to control the enabling and disabling of the pre-charge circuit paths.