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    NON-VOLATILE MEMORY WITH ISOLATION LATCH SHARED BETWEEN DATA LATCH GROUPS
    1.
    发明公开
    NON-VOLATILE MEMORY WITH ISOLATION LATCH SHARED BETWEEN DATA LATCH GROUPS 审中-公开

    公开(公告)号：US20230368852A1

    公开(公告)日：2023-11-16

    申请号：US17745120

    申请日：2022-05-16

    申请人： SanDisk Technologies LLC

    发明人： Kei Kitamura ,  Iris Lu ,  Tai-Yuan Tseng

    IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C7/10

    CPC分类号： G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/24 ,  G11C7/1048 ,  G11C7/1039

    摘要： A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.

    WINDOW PROGRAM VERIFY TO REDUCE DATA LATCH USAGE IN MEMORY DEVICE
    5.
    发明申请
    WINDOW PROGRAM VERIFY TO REDUCE DATA LATCH USAGE IN MEMORY DEVICE 有权

    公开(公告)号：US20220415415A1

    公开(公告)日：2022-12-29

    申请号：US17355615

    申请日：2021-06-23

    申请人： SanDisk Technologies LLC

    发明人： Tai-Yuan Tseng ,  Chia-Kai Chou ,  Iris Lu

    IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C7/06

    摘要： Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.

    Non-volatile memory with isolation latch shared between data latch groups
    6.
    发明授权
    Non-volatile memory with isolation latch shared between data latch groups 有权

    公开(公告)号：US11915769B2

    公开(公告)日：2024-02-27

    申请号：US17745120

    申请日：2022-05-16

    申请人： SanDisk Technologies LLC

    发明人： Kei Kitamura ,  Iris Lu ,  Tai-Yuan Tseng

    IPC分类号： G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    CPC分类号： G11C16/3459 ,  G11C7/1039 ,  G11C7/1048 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26

    摘要： A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.

    SIMULATING MEMORY CELL SENSING FOR TESTING SENSING CIRCUITRY
    7.
    发明公开
    SIMULATING MEMORY CELL SENSING FOR TESTING SENSING CIRCUITRY 审中-公开

    公开(公告)号：US20230187014A1

    公开(公告)日：2023-06-15

    申请号：US17550352

    申请日：2021-12-14

    申请人： SanDisk Technologies LLC

    发明人： Iris Lu ,  Yan Li ,  Ohwon Kwon

    IPC分类号： G11C29/54 ,  G11C7/06

    CPC分类号： G11C29/54 ,  G11C7/065

    摘要： Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.

    TRANSFER LATCH TIERS
    8.
    发明申请
    TRANSFER LATCH TIERS 有权

    公开(公告)号：US20230130365A1

    公开(公告)日：2023-04-27

    申请号：US17507606

    申请日：2021-10-21

    申请人： SanDisk Technologies LLC

    发明人： Iris Lu ,  Tai-Yuan Tseng

    IPC分类号： G11C16/24 ,  G11C16/04 ,  G11C16/26

    摘要： Read and write circuitry, described herein, comprises data latches, each data latch connected to a bit line and arranged in a same column as the bit line; and transfer latches, each transfer latch connected to a data latch and arranged in a same column as the data latch. Further, circuitry described herein is configured to: transfer a word to and from the transfer latches of a first column and the subset of transfer latches of a second column; transfer a first portion of the word between the transfer latches of the first column and data latches of the first column that are connected to the transfer latches of the first column; and transfer a second portion of the word between the subset of transfer latches and data latches of the second column that are connected to the subset of transfer latches.

    NOISE REDUCTION IN SENSE AMPLIFIERS FOR NON-VOLATILE MEMORY
    9.
    发明公开
    NOISE REDUCTION IN SENSE AMPLIFIERS FOR NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20240331741A1

    公开(公告)日：2024-10-03

    申请号：US18346359

    申请日：2023-07-03

    申请人： SanDisk Technologies LLC

    发明人： Iris Lu ,  Yonggang Wu ,  Kou Tei ,  Ohwon Kwon

    IPC分类号： G11C7/10 ,  G11C7/12

    CPC分类号： G11C7/1048 ,  G11C7/1039 ,  G11C7/12

    摘要： Techniques are presented to reduce sense amplifier noise from parasitic capacitances that can affect the internal transfer of a data value from a data latch to a sensing node. To transfer the data value, the sensing node is pre-charged and the data value used to set the control gate voltage on a transistor in a discharge path for the sensing node. In the discharge path, the transistor is connected in series with a switch, so that when the switch is turned on, the data value on the transistor's control gate will determine whether or not the sensing node discharges. To reduce noise in the process, before the data value is used to bias the discharge path transistor's control gate, a node between the transistor and switch is charged. Additionally, a lower voltage level can be used to turn on the discharge path switch.