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    Observing embedded signals of varying clock domains by fowarding signals within a system on a chip concurrently with a logic module clock signal
    12.
    发明授权
    Observing embedded signals of varying clock domains by fowarding signals within a system on a chip concurrently with a logic module clock signal 有权
    通过在逻辑模块时钟信号同时处理芯片上系统内的信号来观察不同时钟域的嵌入信号

    公开(公告)号：US09201448B2

    公开(公告)日：2015-12-01

    申请号：US13536148

    申请日：2012-06-28

    申请人： Sankaran M. Menon ,  Binta M. Patel ,  Bo Jiang ,  Nancy G. Woodbridge

    发明人： Sankaran M. Menon ,  Binta M. Patel ,  Bo Jiang ,  Nancy G. Woodbridge

    IPC分类号： G06F1/12 ,  G06F13/42

    CPC分类号： G06F1/12

    摘要： Observability of internal system-on-chip signals is a difficult problem and it is particularly difficult to observe and debug transactions with different clock domains. However, one embodiment provides observability of internal signals from multiple internal blocks having varying clock domains such as synchronous (common clock) and asynchronous (non common clock) domains. An embodiment provides simultaneous observability of debug data from both synchronous and asynchronous clock domains. An embodiment may also allow sending debug data from both synchronous and asynchronous domains from the SoC. One embodiment outputs internal signals on output pins of the SoC, thereby allowing transactions from one clock domain to be tracked to another clock domain and allowing for the determination of the relationship between the data of differing clock domains. Other embodiments are described herein.

    摘要翻译： 内部片上系统信号的可观察性是一个困难的问题，特别难以观察和调试与不同时钟域的交易。 然而，一个实施例提供了具有变化的时钟域（例如同步（公共时钟））和异步（非公共时钟）域的多个内部块的内部信号的可观察性。 一个实施例提供来自同步和异步时钟域的调试数据的同时可观察性。 一个实施例还可以允许从SoC发送来自同步和异步域的调试数据。 一个实施例在SoC的输出引脚上输出内部信号，从而允许来自一个时钟域的事务被跟踪到另一个时钟域，并允许确定不同时钟域的数据之间的关系。 本文描述了其它实施例。