Method and structure for reducing the incidence of voiding in an underfill layer of an electronic component package
    12.
    发明授权
    Method and structure for reducing the incidence of voiding in an underfill layer of an electronic component package 有权
    用于减少电子部件封装的底部填充层中的空隙发生率的方法和结构

    公开(公告)号:US06320127B1

    公开(公告)日:2001-11-20

    申请号:US09465425

    申请日:1999-12-20

    IPC分类号: H05K506

    摘要: A packaging substrate includes a plurality of bonding pads and a plurality of gutters formed thereon. A die having conductive bumps on an electrically active surface thereof is positioned such that the conductive bumps of the die are electrically connected to the bonding pads of the packaging substrate. An underfill material fills the underfill space between the packaging substrate and the die to complete the structure. The plurality of gutters creates a linear flow front of the underfill material as it flows across the underfill space.

    摘要翻译: 封装基板包括多个接合焊盘和形成在其上的多个沟槽。 在其电活性表面上具有导电凸块的模具被定位成使得模具的导电凸块电连接到封装衬底的焊盘。 底部填充材料填充包装基板和模具之间的底部填充空间以完成该结构。 当底部填充材料流过底部填充空间时,多个水槽产生底部填充材料的线性流动前部。