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公开(公告)号:US11994268B2
公开(公告)日:2024-05-28
申请号:US17988550
申请日:2022-11-16
Applicant: Optovate Limited
Inventor: Jonathan Harrold , Graham J. Woodgate
IPC: H01L25/075 , F21K9/00 , F21K9/64 , F21K9/68 , F21K9/69 , F21K9/90 , F21V5/00 , F21V9/30 , F21V13/04 , G02B19/00 , G02F1/13357 , G09G3/20 , H01L21/268 , H01L21/66 , H01L23/00 , H01L25/16 , H01L33/00 , H01L33/08 , H01L33/50 , H01L33/56 , H01L33/58 , H01L33/60 , H01L33/62 , F21V17/00 , F21Y101/00 , F21Y113/13 , F21Y115/10 , G02F1/1335
CPC classification number: F21V13/04 , F21K9/00 , F21K9/64 , F21K9/68 , F21K9/69 , F21K9/90 , F21V5/007 , F21V9/30 , G02B19/0028 , G02B19/0066 , G02F1/133603 , G02F1/133605 , G09G3/2088 , H01L21/268 , H01L22/20 , H01L24/32 , H01L25/0753 , H01L25/167 , H01L33/0093 , H01L33/0095 , H01L33/08 , H01L33/504 , H01L33/507 , H01L33/56 , H01L33/58 , H01L33/60 , H01L33/62 , F21V17/00 , F21Y2101/00 , F21Y2113/13 , F21Y2115/10 , G02F1/133607 , G02F1/133612 , H01L2224/16225 , H01L2224/73265 , H01L2924/01322 , H01L2924/09701 , H01L2924/12035 , H01L2924/12042 , H01L2924/1301 , H01L2924/13033 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2933/0033 , H01L2933/0041 , H01L2933/005 , H01L2933/0058 , H01L2933/0066 , Y10T29/49117 , H01L2924/3512 , H01L2924/00 , H01L2924/01322 , H01L2924/00 , H01L2924/13033 , H01L2924/00 , H01L2924/1301 , H01L2924/00 , H01L2924/15787 , H01L2924/00 , H01L2924/15788 , H01L2924/00 , H01L2924/12035 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2924/14 , H01L2924/00
Abstract: An illumination apparatus comprises a plurality of LEDs aligned to an array of directional optical elements wherein the LEDs are substantially at the input aperture of respective optical elements. An electrode array is formed on the array of optical elements to provide at least a first electrical connection to the array of LED elements. Advantageously such an arrangement provides low cost and high efficiency from the directional LED array.
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公开(公告)号:US20180331427A1
公开(公告)日:2018-11-15
申请号:US16041382
申请日:2018-07-20
Applicant: Fractus, S.A.
IPC: H01Q9/04 , H01Q9/40 , H01Q9/42 , H01Q13/10 , H01L25/16 , H01Q1/22 , H01L23/66 , H01Q1/36 , H01Q1/38 , H01Q1/40 , H01Q9/26 , H01L23/00
CPC classification number: H01Q9/045 , H01L23/66 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/165 , H01L2223/6677 , H01L2224/05599 , H01L2224/16225 , H01L2224/32225 , H01L2224/45015 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48265 , H01L2224/48464 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/14 , H01L2924/1423 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/207 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H01Q1/22 , H01Q1/2283 , H01Q1/36 , H01Q1/38 , H01Q1/40 , H01Q9/26 , H01Q9/30 , H01Q9/40 , H01Q9/42 , H01Q13/10
Abstract: The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna, each of the five sections or segments forming a pair of angles with each adjacent segment or section, wherein the smaller angle of each of the four pairs of angles between sections or segments is less than 180° (i.e., no pair of sections or segments define a longer straight segment), wherein at least two of the angles are less than 115°, wherein at least two of the angles are not equal, and wherein the curve fits inside a rectangular area the longest edge of which is shorter than one-fifth of the longest free-space operating wavelength of the antenna.
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公开(公告)号:US20180296823A1
公开(公告)日:2018-10-18
申请号:US15944075
申请日:2018-04-03
Applicant: Stryker Corporation
Inventor: Robert A. Brindley , John J. Janik , Edward Chia-Ning Tang , James Bernard Dunlop , Leland Joseph Spangler
CPC classification number: A61N1/05 , A61N1/0553 , A61N1/08 , H01L24/19 , H01L24/20 , H01L2224/04105 , H01L2224/2101 , H01L2224/211 , H01L2224/215 , H01L2224/221 , H01L2224/24227 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H05K1/118 , H05K1/185 , H01L2924/00
Abstract: An implantable electrode array is provided that includes a carrier that is flexible. At least one control module is coupled to the carrier. A shell encases the control module. At least one electrode is coupled to the carrier and is electrically connected to the control module.
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公开(公告)号:US20180272137A1
公开(公告)日:2018-09-27
申请号:US15936495
申请日:2018-03-27
Applicant: Greatbatch Ltd.
Inventor: Keith W. Seitz , Xiaohong Tang , William C. Thiebolt , Jonathan Calamel , Thomas Shi , Thomas Marzano
CPC classification number: A61N1/3754 , C03C8/14 , C04B2237/343 , C04B2237/348 , C04B2237/361 , C04B2237/363 , C04B2237/365 , C04B2237/403 , C04B2237/408 , H01L23/10 , H01L23/15 , H01L24/26 , H01L2924/01006 , H01L2924/01022 , H01L2924/01029 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H05K1/0306 , H05K3/0047 , H05K5/0095
Abstract: Disclosed herein are electrically conductive and hermetic vias disposed within an insulator substrate of a feedthrough assembly and methods for making and using the same. Such aspects of the present invention consequently provide for the miniaturization of feedthrough assemblies inasmuch as the feedthrough components of the present invention are capable of supporting very small and hermetic conductively filled via holes in the absence of additional components, such as, for example, terminal pins, leadwires, and the like.
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5.
公开(公告)号:US20180211896A1
公开(公告)日:2018-07-26
申请号:US15936715
申请日:2018-03-27
Applicant: Micron Technology, Inc.
Inventor: Matt E. Schwab , J. Michael Brooks , David J. Corisis
IPC: H01L23/31 , H01L23/16 , H01L23/492 , H01L23/00 , H01L25/065 , H01L23/36
CPC classification number: H01L23/3128 , H01L23/16 , H01L23/36 , H01L23/4924 , H01L24/06 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/06135 , H01L2224/06136 , H01L2224/16225 , H01L2224/274 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/83192 , H01L2224/838 , H01L2225/0651 , H01L2225/06575 , H01L2225/06589 , H01L2225/06593 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/16235 , H01L2924/16788 , H01L2924/181 , H01L2924/351 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.
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公开(公告)号:US09966504B2
公开(公告)日:2018-05-08
申请号:US15651492
申请日:2017-07-17
Applicant: Sharp Kabushiki Kaisha
Inventor: Masahiro Konishi , Makoto Agatani , Toshio Hata
IPC: H01L33/50 , F21K99/00 , H01L33/62 , H01L33/36 , F21V23/00 , H01L33/38 , H01L33/32 , F21K9/20 , H01L25/075 , H01L33/56 , H01L33/60 , F21K9/00 , H01L33/64 , F21Y115/10 , F21Y105/10 , F21K9/232 , H01L23/00 , F21Y101/00
CPC classification number: H01L33/502 , F21K9/00 , F21K9/20 , F21K9/232 , F21V23/002 , F21Y2101/00 , F21Y2105/10 , F21Y2115/10 , H01L24/45 , H01L25/0753 , H01L33/32 , H01L33/36 , H01L33/38 , H01L33/56 , H01L33/60 , H01L33/62 , H01L33/641 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45169 , H01L2224/48091 , H01L2224/48465 , H01L2224/73265 , H01L2924/01015 , H01L2924/01047 , H01L2924/01068 , H01L2924/01087 , H01L2924/09701 , H01L2924/12041 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: By using a light emitting device including an insulating substrate and a light emitting unit formed on the insulating substrate, the light emitting unit including: a plurality of linear wiring patterns disposed on the insulating substrate in parallel with one another, a plurality of light emitting elements that are mounted between the wiring patterns while being electrically connected to the wiring patterns, and a sealing member for sealing the light emitting elements, as well as a method for manufacturing thereof, it becomes possible to provide a light emitting device that achieves sufficient electrical insulation and has simple manufacturing processes so that it can be manufactured at a low cost, and a method for manufacturing the same.
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公开(公告)号:US09930775B2
公开(公告)日:2018-03-27
申请号:US14255083
申请日:2014-04-17
Applicant: HSIO TECHNOLOGIES, LLC
Inventor: Jim Rathburn
IPC: H01L23/12 , H01L23/00 , H05K1/11 , H05K1/02 , H05K3/46 , G02B6/36 , G02B6/42 , H01L23/31 , H01L23/498 , H01L21/48 , H01L23/60 , H01L25/16
CPC classification number: H05K1/0298 , G02B6/3608 , G02B6/4281 , H01L21/486 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L23/60 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/48 , H01L25/16 , H01L2223/6627 , H01L2224/0401 , H01L2224/08235 , H01L2224/1132 , H01L2224/131 , H01L2224/16225 , H01L2224/16235 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/81192 , H01L2924/00014 , H01L2924/09701 , H01L2924/12042 , H01L2924/12044 , H01L2924/1306 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/381 , H05K1/113 , H05K3/4644 , H05K2201/09563 , H05K2201/096 , H05K2203/0733 , H05K2203/1476 , H01L2924/00 , H01L2224/45099 , H01L2924/014
Abstract: An electrical interconnect including a first circuitry layer with a first surface and a second surface. A first liquid dielectric layer is imaged directly on the first surface of the first circuitry layer to form a first dielectric layer with a plurality of first recesses. Conductive plating substantially fills a plurality of the first recesses to create a plurality of first solid copper conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer. A second liquid dielectric layer is imaged directly on the first dielectric layer to form a second dielectric layer with a plurality of second recesses. Conductive plating substantially fills a plurality of the second recesses to form a plurality of second solid copper conductive pillars electrically coupled to, and extending parallel with, the first conductive pillars. An IC device is electrically coupled to a plurality of the second conductive pillars.
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公开(公告)号:US09887329B2
公开(公告)日:2018-02-06
申请号:US14884718
申请日:2015-10-15
Applicant: Nichia Corporation
Inventor: Motokazu Yamada
IPC: H01L33/60 , H01L23/00 , H01L33/62 , H01L33/00 , H01L33/50 , H01L25/16 , H01L33/52 , H01L25/075 , H01L33/48 , H01L33/54
CPC classification number: H01L33/60 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0753 , H01L25/167 , H01L33/005 , H01L33/483 , H01L33/486 , H01L33/50 , H01L33/52 , H01L33/54 , H01L33/62 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45169 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2224/48228 , H01L2224/49175 , H01L2224/73204 , H01L2224/73265 , H01L2224/83192 , H01L2224/8592 , H01L2224/92247 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01025 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/01042 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01063 , H01L2924/01065 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12035 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2924/181 , H01L2924/3025 , H01L2933/005 , H01L2924/00 , H01L2924/2076 , H01L2224/05599 , H01L2924/00012
Abstract: A light emitting device (100) includes a base member (101), electrically conductive members (102a, 102b) disposed on the base member (101), a light emitting element (104) mounted on the electrically conductive members (102a, 102b), an insulating filler (114) covering at least a portion of surfaces of the electrically conductive members (102a, 102b) where the light emitting element (104) is not mounted, and a light transmissive member (108) covering the light emitting element (104).
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公开(公告)号:US20180033754A1
公开(公告)日:2018-02-01
申请号:US15664158
申请日:2017-07-31
Applicant: Cufer Asset Ltd. L.L.C.
Inventor: Roger Dugas , John Trezza
IPC: H01L23/00 , H01L21/48 , H01L25/18 , H01L25/065 , H01L23/66 , H01L23/552 , H01L23/538 , H01L23/498 , H01L23/488 , H01L23/48 , H01L23/427 , H01L21/768 , H01L21/683 , H01L25/00 , H01S5/042 , H01S5/183 , H01S5/022
CPC classification number: H01L24/11 , H01L21/4853 , H01L21/6835 , H01L21/76898 , H01L23/427 , H01L23/48 , H01L23/481 , H01L23/488 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L23/66 , H01L24/02 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/75 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/68345 , H01L2221/68363 , H01L2221/68368 , H01L2223/6616 , H01L2223/6622 , H01L2224/02372 , H01L2224/0401 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/11912 , H01L2224/13012 , H01L2224/13021 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13099 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13184 , H01L2224/1358 , H01L2224/136 , H01L2224/13609 , H01L2224/16146 , H01L2224/16237 , H01L2224/24226 , H01L2224/45111 , H01L2224/75 , H01L2224/75305 , H01L2224/81001 , H01L2224/81011 , H01L2224/81054 , H01L2224/81136 , H01L2224/81193 , H01L2224/81203 , H01L2224/81204 , H01L2224/81825 , H01L2224/81894 , H01L2224/83102 , H01L2224/92125 , H01L2225/06513 , H01L2225/06524 , H01L2225/06531 , H01L2225/06534 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2225/06593 , H01L2225/06596 , H01L2924/00013 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01S5/02272 , H01S5/02276 , H01S5/0422 , H01S5/0425 , H01S5/183 , H01S5/18308 , H01S2301/176 , H01L2924/00014 , H01L2924/00
Abstract: A method for use with multiple chips, each respectively having a bonding surface including electrical contacts and a surface on a side opposite the bonding surface involves bringing a hardenable material located on a body into contact with the multiple chips, hardening the hardenable material so as to constrain at least a portion of each of the multiple chips, moving the multiple chips from a first location to a second location, applying a force to the body such that the hardened, hardenable material will uniformly transfer a vertical force, applied to the body, to the chips so as to bring, under pressure, a bonding surface of each individual chip into contact with a bonding surface of an element to which the individual chips will be bonded, at the second location, without causing damage to the individual chips, element, or bonding surface.
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公开(公告)号:US09847253B2
公开(公告)日:2017-12-19
申请号:US12757750
申请日:2010-04-09
Applicant: Byung Tai Do , Heap Hoe Kuan , Seng Guan Chow
Inventor: Byung Tai Do , Heap Hoe Kuan , Seng Guan Chow
IPC: H01L21/00 , H01L21/768 , H01L23/31 , H01L23/48 , H01L23/00 , H01L25/03 , H01L25/065 , H01L25/10 , H01L23/538
CPC classification number: H01L21/76898 , H01L23/3128 , H01L23/481 , H01L23/5389 , H01L24/18 , H01L24/19 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/04042 , H01L2224/05554 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/18 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45139 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2225/06513 , H01L2225/06524 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10161 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/18162 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
Abstract: A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.
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