公开(公告)号：US20110205798A1

公开(公告)日：2011-08-25

申请号：US13068066

申请日：2011-05-02

申请人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Tomoya Saito ,  Yoshitaka Baba

发明人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Tomoya Saito ,  Yoshitaka Baba

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C16/28

CPC分类号： G11C16/0475

摘要： The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.

摘要翻译： 本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新颖操作方法。 在本发明的第一实施例中，替代控制栅极被设置在相同的电压。 在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。 在两个实施例中，位线和字门被用于寻址选定的存储单元。

公开(公告)号：US07936604B2

公开(公告)日：2011-05-03

申请号：US11215418

申请日：2005-08-30

申请人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Tomoya Saito ,  Yoshitaka Baba

发明人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Tomoya Saito ,  Yoshitaka Baba

IPC分类号： G11C11/34

CPC分类号： G11C16/0475

摘要： The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.

摘要翻译： 本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新颖操作方法。 在本发明的第一实施例中，替代控制栅极被设置在相同的电压。 在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。 在两个实施例中，位线和字门被用于寻址选定的存储单元。

公开(公告)号：US06631088B2

公开(公告)日：2003-10-07

申请号：US10190634

申请日：2002-07-08

申请人： Seiki Ogura ,  Tomoya Saito ,  Tomoko Ogura

发明人： Seiki Ogura ,  Tomoya Saito ,  Tomoko Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24

摘要： In the present invention a twin MONOS metal bit line array is read and programmed using a three dimensional programming method with X, Y and Z dimensions. The word line address is the X address. The control gate line address is a function of the X and Z addresses, and the bit line address is a function of the Y and Z addresses. Because the bit lines and the control gate lines of the memory array are orthogonal a single cell can be erased with an adjacent memory, having the same selected bit and control gate lines, being inhibited from erase by application of the proper voltages to unselected word, control gate and bit lines.

摘要翻译： 在本发明中，使用具有X，Y和Z尺寸的三维编程方法来读取和编程双MONOS金属位线阵列。 字线地址是X地址。 控制栅极线地址是X和Z地址的函数，位线地址是Y和Z地址的函数。 由于存储器阵列的位线和控制栅极线是正交的，所以可以通过将具有相同的选择位和控制栅极线的相邻存储器与适当的电压施加到未选择字来禁止单个单元的擦除， 控制门和位线。

公开(公告)号：US20070047307A1

公开(公告)日：2007-03-01

申请号：US11215418

申请日：2005-08-30

申请人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Tomoya Saito ,  Yoshitaka Baba

发明人： Tomoko Ogura ,  Nori Ogura ,  Seiki Ogura ,  Tomoya Saito ,  Yoshitaka Baba

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： The present invention provides a novel operational method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.

摘要翻译： 本发明提供了一种用于高速应用的双MONOS金属钻头或扩散钻头结构的新颖操作方法。 在本发明的第一实施例中，替代控制栅极被设置在相同的电压。 在本发明的第二实施例中，所有的控制栅极都从一开始就被设定为工作电压。 在两个实施例中，位线和字门被用于寻址选定的存储单元。

公开(公告)号：US07352033B2

公开(公告)日：2008-04-01

申请号：US11215528

申请日：2005-08-30

申请人： Kimihiro Satoh ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Yoshitaka Baba

发明人： Kimihiro Satoh ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Yoshitaka Baba

IPC分类号： H01L29/772

CPC分类号： G11C16/08 ,  G11C16/0466 ,  G11C16/16 ,  H01L29/792

摘要： The invention provides a metal bit structure of Twin MONOS memory cell with large channel width and its operational method for high-speed applications using a metal bit array.

摘要翻译： 本发明提供了具有大通道宽度的双MONOS存储单元的金属钻头结构及其使用金属钻头阵列的高速应用的操作方法。

公开(公告)号：US20070047309A1

公开(公告)日：2007-03-01

申请号：US11215528

申请日：2005-08-30

申请人： Kimihiro Satoh ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Yoshitaka Baba

发明人： Kimihiro Satoh ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Yoshitaka Baba

IPC分类号： G11C16/04

CPC分类号： G11C16/08 ,  G11C16/0466 ,  G11C16/16 ,  H01L29/792

摘要： The invention provides a metal bit structure of Twin MONOS memory cell with large channel width and its operational method for high-speed applications using a metal bit array.

摘要翻译： 本发明提供了具有大通道宽度的双MONOS存储单元的金属钻头结构及其使用金属钻头阵列的高速应用的操作方法。

公开(公告)号：US08633544B2

公开(公告)日：2014-01-21

申请号：US12079966

申请日：2008-03-31

申请人： Kimihiro Satoh ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Yoshitaka Baba

发明人： Kimihiro Satoh ,  Tomoko Ogura ,  Ki-Tae Park ,  Nori Ogura ,  Yoshitaka Baba

IPC分类号： H01L29/772

CPC分类号： G11C16/08 ,  G11C16/0466 ,  G11C16/16 ,  H01L29/792

摘要： A stitch area configuration for word gates and control gates of a twin MONOS metal bit array comprises control gates on sidewalls of the word gates wherein the word gates and control gates run in parallel. Control gate poly contacts contact each of the control gates aligned in a row at the stitch area perpendicular to the control gates. Two word gate poly contacts at the stitch area contact alternating word gates. Also provided are bit lines, word line and control gate decoders and drivers, a bit line decoder, a bit line control circuit, and a chip controller to control the memory array. The invention also provides twin MONOS metal bit array operations comprising several control gates driven by one control gate driver circuit and one word gate driven by one word gate driver circuit, as well as erase inhibit and block erase.

摘要翻译： 双MONOS金属位阵列的字栅和控制栅的针迹区域配置包括在字门的侧壁上的控制栅极，其中字栅和控制栅并联运行。 控制栅极多晶硅触点在垂直于控制栅极的针脚区域处接触排列成一排的控制栅极。 缝合区域的两个字门多晶硅接点交替字门。 还提供了位线，字线和控制门解码器和驱动器，位线解码器，位线控制电路和用于控制存储器阵列的芯片控制器。 本发明还提供双MONOS金属位阵列操作，其包括由一个控制栅极驱动电路驱动的多个控制栅极和由一个字栅极驱动器电路驱动的一个字栅极以及擦除禁止和块擦除。

公开(公告)号：US20100261324A1

公开(公告)日：2010-10-14

申请号：US12802894

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： H01L21/336

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。

公开(公告)号：US20100259985A1

公开(公告)日：2010-10-14

申请号：US12802895

申请日：2010-06-16

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

公开(公告)号：US20080101117A1

公开(公告)日：2008-05-01

申请号：US11982172

申请日：2007-11-01

申请人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

发明人： Tomoko Ogura ,  Seiki Ogura ,  Nori Ogura

IPC分类号： G11C16/04 ,  H01L21/336

CPC分类号： G11C16/0466 ,  G11C16/0475 ,  H01L27/115

摘要： A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

摘要翻译： 非易失性陷阱电荷存储单元选择在可编程逻辑应用中使用的逻辑互连晶体管，例如FPGA。 非挥发性捕获电荷元件是位于控制栅极下方并位于半导体衬底表面上的氧化物之上的绝缘体。 优选实施例是集成器件，其包括夹在两个非易失性陷阱电荷存储部分之间的字门部分，其中该集成器件连接在高偏压，低偏压和输出之间。 输出由连接到字栅极下方的通道的扩散形成。 两个存储部分的编程状态确定高偏压或低偏压是否耦合到连接到输出扩散的逻辑互连晶体管。