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11.发明授权Hybrid scan-based delay testing technique for compact and high fault coverage test set 失效基于混合扫描的延迟测试技术，用于紧凑型和高故障覆盖测试公开(公告)号：US07313743B2
公开(公告)日：2007-12-25
申请号：US10653959
申请日：2003-09-04
Applicant: Seongmoon Wang , Xiao Liu , Srimat T. Chakradhar
Inventor： Seongmoon Wang , Xiao Liu , Srimat T. Chakradhar
IPC: G01R31/317 , G01R31/316
CPC classification number: G01R31/31858 , G11B20/1816
Abstract: A scan-based method for testing delay faults in a circuit comprising controlling a subset of state inputs of the circuit by a skewed-load approach and controlling all inputs other than said subset of state inputs by a broad-side approach.
Abstract translation: 一种用于测试电路中的延迟故障的基于扫描的方法，包括通过偏斜负载方法控制所述电路的状态输入的子集，并且通过广泛方法控制除所述状态输入子集之外的所有输入。
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12.发明授权Test pattern compression with pattern-independent design-independent seed compression 失效测试模式压缩与模式无关的独立于设计的种子压缩公开(公告)号：US07302626B2
公开(公告)日：2007-11-27
申请号：US11095222
申请日：2005-03-31
Applicant: Kedarnath Balakrishnan , Seongmoon Wang , Srimat T. Chakradhar
Inventor： Kedarnath Balakrishnan , Seongmoon Wang , Srimat T. Chakradhar
IPC: G01R31/28
CPC classification number: G01R31/318335 , G01R31/318371
Abstract: The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set.
Abstract translation: 本发明涉及具有改进的解压缩引擎的逻辑测试架构，其以独立于测试模式集的方式压缩线性测试模式发生器的种子。
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公开(公告)号：US20060101316A1
公开(公告)日：2006-05-11
申请号：US10985599
申请日：2004-11-10
Applicant: Seongmoon Wang , Srimat Chakradhar , Chia-Tso Chao
Inventor： Seongmoon Wang , Srimat Chakradhar , Chia-Tso Chao
IPC: G01R31/28
CPC classification number: G01R31/318547
Abstract: An improved test output compaction architecture and method is disclosed that takes advantage of a response shaper in order to minimize masking of faults during compaction.
Abstract translation: 公开了一种改进的测试输出压缩架构和方法，其利用响应整形器来最小化压缩期间的故障屏蔽。
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公开(公告)号：US07610539B2
公开(公告)日：2009-10-27
申请号：US12265330
申请日：2008-11-05
Applicant: Kedarnath Balakrishnan , Seongmoon Wang , Wenlong Wei , Srimat T. Chakradhar
Inventor： Kedarnath Balakrishnan , Seongmoon Wang , Wenlong Wei , Srimat T. Chakradhar
CPC classification number: G01R31/31921
Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.
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15.发明申请Method for Blocking Unknown Values in Output Response of Scan Test Patterns for Testing Circuits 失效阻止测试电路扫描测试模式输出响应中未知值的方法公开(公告)号：US20090210762A1
公开(公告)日：2009-08-20
申请号：US12034088
申请日：2008-02-20
Applicant: Seongmoon Wang , Srimat T. Chakradhar
Inventor： Seongmoon Wang , Srimat T. Chakradhar
IPC: G01R31/28
CPC classification number: G01R31/318547
Abstract: A method includes compressing control patterns describing values required at the control signals of blocking logic gates, by linear feedback shift register LFSR reseeding; bypassing blocking logic gates for some groups of scan chains that do not capture unknown values in output response of scan test patterns for testing circuits; and reducing numbers of specified bits in densely specified ones of the control patterns for further reducing the size of a seed of the LFSR.
Abstract translation: 一种方法包括通过线性反馈移位寄存器LFSR重新进给来压缩描述阻塞逻辑门控制信号所需的值的控制模式; 绕过阻塞逻辑门，用于扫描链的扫描测试图形的输出响应中未捕获未知值的扫描链组; 并且减少密集指定的控制模式中的指定位的数量，以进一步减小LFSR的种子的大小。
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Patent Agency Ranking
公开(公告)号：US07562321B2
公开(公告)日：2009-07-14
申请号：US11567955
申请日：2006-12-07
Applicant: Seongmoon Wang , Srimat T. Chakradhar
Inventor： Seongmoon Wang , Srimat T. Chakradhar
IPC: G06F17/50
CPC classification number: G06F17/5045 , G01R31/31704
Abstract: Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the structured ASIC is identified and then a test point is inserted at the unused cell of the structured ASIC (e.g., if the unused cell is neighboring at least one used cell of the structured ASIC).
Abstract translation: 确定结构化专用集成电路（ASIC）中的测试点位置包括使用结构化ASIC的一个或多个未使用的单元。 特别地，识别出结构化ASIC的未使用单元，然后将测试点插入到结构化ASIC的未使用单元（例如，如果未使用单元与结构化ASIC的至少一个使用单元相邻）。
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公开(公告)号：US20090119563A1
公开(公告)日：2009-05-07
申请号：US12265300
申请日：2008-11-05
Applicant: Kedarnath Balakrishnan , Seongmoon Wang , Wenlong Wei , Srimat T. Chakradhar
Inventor： Kedarnath Balakrishnan , Seongmoon Wang , Wenlong Wei , Srimat T. Chakradhar
CPC classification number: G01R31/31921
Abstract: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.
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18.发明申请Test Data Compression Method for System-On-Chip Using Linear-Feedback Shift Register Reseeding 失效使用线性反馈移位寄存器重新接收的片上系统的测试数据压缩方法公开(公告)号：US20080065940A1
公开(公告)日：2008-03-13
申请号：US11839190
申请日：2007-08-15
Applicant: Zhanglei Wang , Seongmoon Wang
Inventor： Zhanglei Wang , Seongmoon Wang
IPC: G06F11/25
CPC classification number: G06F11/2236
Abstract: A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.
Abstract translation: 一种方法包括在片上系统电路中获得多个核心的等效核心，以及应用线性反馈移位寄存器LFSR重新进给来压缩等效核心的测试数据。
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公开(公告)号：US07313746B2
公开(公告)日：2007-12-25
申请号：US11277782
申请日：2006-03-29
Applicant: Chia-Tso Chao , Seongmoon Wang , Srimat T. Chakradhar
Inventor： Chia-Tso Chao , Seongmoon Wang , Srimat T. Chakradhar
IPC: G01R31/28
CPC classification number: G01R31/318547
Abstract: A spatial compactor design and technique for the compaction of test response data is herein disclosed which advantageously provides a scan-out response with multiple opportunities to be observed on different output channels in one to several scan-shift cycles.
Abstract translation: 本文公开了用于压缩测试响应数据的空间压实机设计和技术，其有利地提供扫描输出响应，其具有在一到多个扫描移位周期中在不同输出通道上观察到的多个机会。
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公开(公告)号：US20070136700A1
公开(公告)日：2007-06-14
申请号：US11567955
申请日：2006-12-07
Applicant: Seongmoon Wang , Srimat Chakradhar
Inventor： Seongmoon Wang , Srimat Chakradhar
IPC: G06F17/50
CPC classification number: G06F17/5045 , G01R31/31704
Abstract: Determining a test point location in a structured application specific integrated circuit (ASIC) includes using one or more unused cells of the structured ASIC. In particular, an unused cell of the structured ASIC is identified and then a test point is inserted at the unused cell of the structured ASIC (e.g., if the unused cell is neighboring at least one used cell of the structured ASIC).
Abstract translation: 确定结构化专用集成电路（ASIC）中的测试点位置包括使用结构化ASIC的一个或多个未使用的单元。 特别地，识别出结构化ASIC的未使用单元，然后将测试点插入到结构化ASIC的未使用单元（例如，如果未使用单元与结构化ASIC的至少一个使用单元相邻）。
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