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135 条记录 (耗时 0.024 秒)

    Logic circuit and its forming method
    11.
    发明授权
    Logic circuit and its forming method 失效
    逻辑电路及其形成方法

    公开(公告)号：US06696864B2

    公开(公告)日：2004-02-24

    申请号：US10266773

    申请日：2002-10-09

    申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

    发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

    IPC分类号： H03K19094

    CPC分类号： G06F17/505 ,  H03K19/1737

    摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

    摘要翻译： 本申请提出了一种新的逻辑电路，包括第一选择器（S1），其中控制输入S由第一输入信号（IN1）控制，输入I1或I0由第二输入信号（IN2）控制，输出 O连接到第一节点（N1），并且第三选择器（S3），其中控制输入S由第一节点（N1）控制，输入I1由第三输入信号（IN3）控制，输入 I0由第一输入信号（IN1）控制，输出端连接到第一输出信号（OUT1）。

    Semiconductor integrated circuit
    13.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06388474B2

    公开(公告)日：2002-05-14

    申请号：US09860587

    申请日：2001-05-21

    申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

    IPC分类号： H03K19094

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

    摘要翻译： 对于第一和第二通过晶体管电路（PT1，PT2）之间的关系，前级的输出信号被提供给后级的栅极，并且对于第二和第三通过晶体管电路之间的关系 （PT2，PT3），将前级的输出信号提供给后级的源极 - 漏极路径。 第一通过晶体管电路（PT1）在第一输入节点（In1）和第二输入节点（In2）上接收逻辑上彼此独立的第一输入信号和第二输入信号。 该逻辑电路需要较少数量的晶体管，并且能够降低功耗并延迟并完成复杂的逻辑功能。

    Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit
    15.
    发明授权
    Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit 失效
    包括组合传输晶体管和CMOS电路的逻辑电路和合成逻辑电路的方法

    公开(公告)号：US06820242B2

    公开(公告)日：2004-11-16

    申请号：US10178216

    申请日：2002-06-25

    申请人： Shunzo Yamashita ,  Kazuo Yano

    发明人： Shunzo Yamashita ,  Kazuo Yano

    IPC分类号： G06F1750

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： To produce a logic circuit with excellent characteristics including area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function. Respective nodes are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. A pass transistor selector operating as a NAND or NOR logic with any one of its two inputs, excluding the control input, being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value.

    摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生具有优异特性（包括面积，延迟时间和功耗）的逻辑电路，从布尔函数创建二进制决策图。 各节点映射到2输入1输出1控制输入通道晶体管选择器，以合成传输晶体管逻辑电路。 用作NAND或NOR逻辑的传输晶体管选择器被替换为操作为NAND或NOR逻辑的CMOS栅极，其两个输入中的任一个（不包括控制输入）被固定为逻辑常数“1”或“0” 如果通过替换获得的预定电路特性的值更接近于最佳值，则在逻辑上等效于通过晶体管选择器。

    Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit
    16.
    发明授权
    Logic circuit including combined pass transistor and CMOS circuits and a method of synthesizing the logic circuit 失效
    包括组合传输晶体管和CMOS电路的逻辑电路和合成逻辑电路的方法

    公开(公告)号：US06433588B1

    公开(公告)日：2002-08-13

    申请号：US09940597

    申请日：2001-08-29

    申请人： Shunzo Yamashita ,  Kazuo Yano

    发明人： Shunzo Yamashita ,  Kazuo Yano

    IPC分类号： H03K19094

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

    摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生电路特性优异的逻辑电路，其面积，延迟时间和功率消耗，从布尔函数创建二进制决策图，并将该图的各个节点映射 转换为2输入，1输出，1路控制输入通道晶体管选择器，合成传输晶体管逻辑电路。 在传输晶体管逻辑电路中，作为NAND或NOR逻辑的传输晶体管选择器，其两个输入中的任何一个不包括固定在逻辑常数“1”或“0”的控制输入，被替换为CMOS门 如果通过替换获得的预定电路特性的值更接近于最佳值，逻辑上等效于通过晶体管选择器的NAND或NOR逻辑（如果所得到的逻辑电路的面积，延迟时间或功耗比原始通道小 晶体管逻辑电路）。

    Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit
    17.
    发明授权
    Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit 有权
    包括组合传输晶体管和CMOS电路的逻辑电路和合成逻辑电路的方法

    公开(公告)号：US06313666B1

    公开(公告)日：2001-11-06

    申请号：US09331780

    申请日：1999-06-24

    申请人： Shunzo Yamashita ,  Kazuo Yano

    发明人： Shunzo Yamashita ,  Kazuo Yano

    IPC分类号： H03K19094

    CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

    摘要： In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-inut, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass tansistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

    摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生电路特性优异的逻辑电路，其面积，延迟时间和功率消耗，从布尔函数创建二进制决策图，并将该图的各个节点映射 成为2-inut，1输出，1控制输入通道晶体管选择器，以合成传输晶体管逻辑电路。 在传输晶体管逻辑电路中，作为NAND或NOR逻辑的传输晶体管选择器，其两个输入中的任何一个不包括固定在逻辑常数“1”或“0”的控制输入，被替换为CMOS门 如果通过替换获得的预定电路特性的值更接近于最佳值（如果所得到的逻辑电路的面积，延迟时间或功耗比原始通路小，则逻辑上等效于通过转换器选择器的NAND或NOR逻辑） 晶体管逻辑电路）。

    Design method of a logic circuit
    18.
    发明授权
    Design method of a logic circuit 失效

    公开(公告)号：US06609244B2

    公开(公告)日：2003-08-19

    申请号：US09931879

    申请日：2001-08-20

    申请人： Naoki Kato ,  Kazuo Yano ,  Hidetoshi Chikata ,  Shunzo Yamashita

    发明人： Naoki Kato ,  Kazuo Yano ,  Hidetoshi Chikata ,  Shunzo Yamashita

    IPC分类号： G06F1750

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： Even if only logic circuits described in HDL are distributed over a network, if the logic synthesis ability is insufficient, the overall design capability cannot be enhanced; e.g., a sufficient performance of a gate level logic circuit cannot be attained, or it takes a long time to complete logic synthesis. Considering design skills for logic synthesis are considered as property, the invention enables distribution of design skills between a plurality of design sites over a network interconnecting computers. Charges for a design skill are set for the rates of improvement to the performance of the logic circuit that was refined by the design skill. Desired circuit performance can be attained in a shorter period by shortening the design phases in which an RTL logic circuit is supplied as input and by logic synthesis thereon, a gate level logic circuit is output.

    Logic circuit design method and cell library for use therewith
    19.
    发明授权
    Logic circuit design method and cell library for use therewith 失效

    公开(公告)号：US06651223B2

    公开(公告)日：2003-11-18

    申请号：US10287599

    申请日：2002-11-05

    申请人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

    发明人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

    IPC分类号： G06F1750

    CPC分类号： G06F17/505

    摘要： A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.

    Logic circuit design method and cell library for use therewith
    20.
    发明授权
    Logic circuit design method and cell library for use therewith 失效

    公开(公告)号：US06505322B2

    公开(公告)日：2003-01-07

    申请号：US09904661

    申请日：2001-07-16

    申请人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

    发明人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

    IPC分类号： G06F1750

    CPC分类号： G06F17/505

    摘要： A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.