公开(公告)号：US06651223B2

公开(公告)日：2003-11-18

申请号：US10287599

申请日：2002-11-05

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.

公开(公告)号：US06505322B2

公开(公告)日：2003-01-07

申请号：US09904661

申请日：2001-07-16

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Naoki Kato

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A method, system, and library for generating high-speed logic circuits with reduced path depths even in cases when a critical path diverges into a plurality of paths that eventually converge. By replacing the gates of a logic circuit by selectors with two inputs and one output, a selector-based circuit is generated where a local circuit between the path divergence node and convergence node is detected. The stages of the critical path are reduced by replacing the local circuit by a logically equivalent selector with two inputs and one output; wherein one input of the selector is controlled by a circuit formed by inputting a logical value of “0” to the divergence node from which the local circuit is developed and a second input of the selector is controlled by a circuit formed by inputting a logical value of “1” to the divergence node.

公开(公告)号：US06313665B1

公开(公告)日：2001-11-06

申请号：US09402648

申请日：2000-02-03

申请人： Yasuhiko Sasaki ,  Kunihito Rikino ,  Kazuo Yano ,  Shunzo Yamashita

发明人： Yasuhiko Sasaki ,  Kunihito Rikino ,  Kazuo Yano ,  Shunzo Yamashita

IPC分类号： H01L2710

CPC分类号： H03K19/1737 ,  H01L27/0207 ,  H01L27/11898

摘要： The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

摘要翻译： 传输晶体管逻辑电路单元的I / O端子位置分布在单元中，输出放大器设置在单元的端部，传输晶体管电路沿电位线延伸的方向排列， 信号极性反转电路布置在单元中，并且阱的布置不同于传统CMOS逻辑电路的布置。

公开(公告)号：US6049232A

公开(公告)日：2000-04-11

申请号：US225291

申请日：1999-01-05

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： G06F17/50 ,  H03K19/173 ,  H03K19/0948

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： For the relation between the first and second pass-transistor circuits (PT1, PT2), the output signal of the preceding-stage is supplied to the gate of the succeeding-stage, and for the relation between the second and third pass-transistor circuits (PT2, PT3), the output signal of the preceding-stage is supplied to the source-drain path of the succeeding-stage. The first pass-transistor circuit (PT1) receives on its first input node (In1) and second input node (In2) the first input signal and the second input signal that are logically independent from each other. This logic circuit requires a smaller number of transistors and is capable of reducing the power consumption and delay and accomplishing an intricate logic function.

公开(公告)号：US5712792A

公开(公告)日：1998-01-27

申请号：US633486

申请日：1996-04-17

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki ,  Koichi Seki

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki ,  Koichi Seki

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： In order to effectively explore a binary decision diagram for synthesizing a logic circuit, a tentative circuit comprised of AND gates and OR gates is synthesized from a logic function. The number of gates in this circuit to which two input variables are simultaneously associated are counted and used as correlation between the two input variables. A correlation matrix for correlation among all of the input variables is generated. The input variables are sequentially grouped from a set of input variables with strongest correlation in the correlation matrix: These groups are registered into a correlation tree, and an intergroup correlation tree is produced. These groups are sequentially selected from a group with the least correlation, and the intragroup order of the selected group is changed from one to another. A binary decision diagram is explored which satisfies the most appropriate condition in that group (such as the minimum number of nodes, the minimum delay, and the minimum area). The above processes repeated for all groups. Each node of the binary decision diagram thus obtained is substituted by a selector and each selector circuit is substituted by a circuit of a transistor level.

摘要翻译： 为了有效地研究用于合成逻辑电路的二进制判定图，从逻辑功能合成了由与门和或门组成的暂定电路。 两个输入变量同时关联的该电路中的门数被计数并用作两个输入变量之间的相关。 生成所有输入变量之间相关的相关矩阵。 输入变量从相关矩阵中具有最强相关性的一组输入变量顺序分组：将这些组注册到相关树中，并产生一个组间相关树。 从具有最小相关性的组中顺序地选择这些组，并且所选择的组的组内顺序从一个改变为另一组。 探讨了满足该组中最合适条件（如最小节点数，最小延迟和最小面积）的二进制决策图。 上述过程对所有组重复。 由此获得的二进制判定图的每个节点由选择器代替，并且每个选择器电路被晶体管电平的电路代替。

公开(公告)号：US06845349B1

公开(公告)日：2005-01-18

申请号：US09659735

申请日：2000-09-11

申请人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

发明人： Yasuhiko Sasaki ,  Kazuo Yano ,  Shunzo Yamashita ,  Koichi Seki

IPC分类号： G06F17/50 ,  H03K19/173 ,  G06G7/62

CPC分类号： H03K19/1737 ,  G06F17/505 ,  H03K19/1736

摘要： A program for automatically designing a logic circuit used for a method of designing a pass transistor circuit, by which the number of required transistors, delay time, power consumption and chip area of the pass transistor circuit is reduced. The program executes the following steps: a) receiving inputted logic functions which define the logical relationship between the inputs and the outputs, and an inputted target specification, b) generating a binary decision diagram from part of the logic functions received at (a), c) replacing the diagram nodes formed at (b) with pass transistor circuit, d) judging whether or not the simulation characteristics of the pass transistor circuit described in (c) meets the target specification described in (a), and executing the following steps when the judgment is “no”, e) replacing part of the diagram generated by the procedure described in (b) with another diagram, f) allocating a new binary decision diagram to the control inputs of the nodes of the replaced diagram prepared at (e), and g) repeating the steps (c) and (d) for the diagram prepared at (f).

摘要翻译： 用于自动设计用于设计传输晶体管电路的方法的逻辑电路的程序，由此降低了所需晶体管的数量，延迟时间，功耗以及传输晶体管电路的芯片面积。 该程序执行以下步骤：a）接收定义输入和输出之间的逻辑关系的输入逻辑功能以及输入的目标规范，b）从（a）中接收的部分逻辑函数生成二进制判定图， c）用传统晶体管电路代替（b）形成的图形节点，d）判断（c）中描述的传输晶体管电路的仿真特性是否满足（a）中描述的目标规范，并执行以下步骤 当判断为“否”时，e）用另一个图替换由（b）中描述的过程产生的图的一部分，f）将新的二进制决策图分配给在 e），g）对（f）制备的图重复步骤（c）和（d）。

公开(公告)号：US06820242B2

公开(公告)日：2004-11-16

申请号：US10178216

申请日：2002-06-25

申请人： Shunzo Yamashita ,  Kazuo Yano

发明人： Shunzo Yamashita ,  Kazuo Yano

IPC分类号： G06F1750

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： To produce a logic circuit with excellent characteristics including area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function. Respective nodes are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. A pass transistor selector operating as a NAND or NOR logic with any one of its two inputs, excluding the control input, being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value.

摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生具有优异特性（包括面积，延迟时间和功耗）的逻辑电路，从布尔函数创建二进制决策图。 各节点映射到2输入1输出1控制输入通道晶体管选择器，以合成传输晶体管逻辑电路。 用作NAND或NOR逻辑的传输晶体管选择器被替换为操作为NAND或NOR逻辑的CMOS栅极，其两个输入中的任一个（不包括控制输入）被固定为逻辑常数“1”或“0” 如果通过替换获得的预定电路特性的值更接近于最佳值，则在逻辑上等效于通过晶体管选择器。

公开(公告)号：US06486708B2

公开(公告)日：2002-11-26

申请号：US10122385

申请日：2002-04-16

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

IPC分类号： H03K19094

CPC分类号： G06F17/505 ,  H03K19/1737

摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

公开(公告)号：US06433588B1

公开(公告)日：2002-08-13

申请号：US09940597

申请日：2001-08-29

申请人： Shunzo Yamashita ,  Kazuo Yano

发明人： Shunzo Yamashita ,  Kazuo Yano

IPC分类号： H03K19094

CPC分类号： H03K19/1736 ,  G06F17/505 ,  H03K19/1737

摘要： In order to produce a logic circuit excellent in circuit characteristics which are area, delay time and power consumption by combining pass transistor logic circuits and CMOS logic circuits, a binary decision diagram is created from a Boolean function, and respective nodes of the diagram are mapped into 2-input, 1-output, 1-control input pass transistor selectors to synthesize a pass transistor logic circuit. In the pass transistor logic circuit, a pass transistor selector operating as a NAND or NOR logic with any one of its two inputs excluding the control input being fixed to a logical constant “1” or “0” is replaced with a CMOS gate operating as a NAND or NOR logic logically equivalent to the pass transistor selector if the value of a predetermined circuit characteristic obtained by the replacement is closer to an optimal value (if the resulting logic circuit is smaller in area, delay time or power consumption than the original pass transistor logic circuit).

摘要翻译： 为了通过组合传输晶体管逻辑电路和CMOS逻辑电路来产生电路特性优异的逻辑电路，其面积，延迟时间和功率消耗，从布尔函数创建二进制决策图，并将该图的各个节点映射 转换为2输入，1输出，1路控制输入通道晶体管选择器，合成传输晶体管逻辑电路。 在传输晶体管逻辑电路中，作为NAND或NOR逻辑的传输晶体管选择器，其两个输入中的任何一个不包括固定在逻辑常数“1”或“0”的控制输入，被替换为CMOS门 如果通过替换获得的预定电路特性的值更接近于最佳值，逻辑上等效于通过晶体管选择器的NAND或NOR逻辑（如果所得到的逻辑电路的面积，延迟时间或功耗比原始通道小 晶体管逻辑电路）。

公开(公告)号：US06323690B1

公开(公告)日：2001-11-27

申请号：US09610697

申请日：2000-07-05

申请人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

发明人： Shunzo Yamashita ,  Kazuo Yano ,  Yasuhiko Sasaki

IPC分类号： H03K19094

CPC分类号： G06F17/505 ,  H03K19/1737

摘要： This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).