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公开(公告)号：US10727845B1
公开(公告)日：2020-07-28
申请号：US16451752
申请日：2019-06-25
Applicant: Silicon Laboratories Inc.
Inventor： Krishnan Balakrishnan , James D. Barnette
Abstract: A PLL uses a virtual clock signal during holdover and/or startup to maintain a closed loop for the PLL and allow for phase/frequency adjustment of the PLL output through the feedback divider during holdover/startup when reference clock(s) supplied to the PLL are unavailable. The virtual clock signal is a series of digital values separated by a time period, where the digital values indicate transitions of the virtual clock signal and the time period corresponds to a period of the virtual clock signal. A selector circuit selects as a digital reference clock signal the virtual clock signal in a holdover or startup mode and another reference clock signal in normal operation.
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公开(公告)号：US10826507B1
公开(公告)日：2020-11-03
申请号：US16404056
申请日：2019-05-06
Applicant: Silicon Laboratories Inc.
Inventor： Xue-Mei Gong , James D. Barnette
Abstract: A clock product includes a phase-locked loop configured to generate an output clock signal based on an input digital value and a feedback digital value. The input digital value corresponds to a first clock edge of a frequency-divided input clock signal and the feedback digital value corresponds to a second clock edge of a feedback clock signal. The clock product includes an input fractional divider configured to generate the input digital value based on an input clock signal, a divider value, and an input clock period digital code corresponding to a period of the input clock signal.
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公开(公告)号：US10819354B2
公开(公告)日：2020-10-27
申请号：US16580161
申请日：2019-09-24
Applicant: Silicon Laboratories Inc.
Inventor： Kannanthodath V. Jayakumar , James D. Barnette
Abstract: A frequency monitoring circuit monitors a frequency offset between a first clock signal and a second clock signal. The frequency monitoring circuit includes a first moving average filter with a plurality of cascaded filter stages and a second moving average filter with a plurality of cascaded filter stages. A plurality of error detection circuits detect if differences between respective cascaded filter stages of the moving average filters exceed respective thresholds. The frequency monitoring circuit asserts a frequency error signal if any of the error detection circuits detect an error. A phase monitoring circuit asserts a phase error if a phase error is above a phase error threshold. The frequency error signal and the phase error signals are combined as a loss of lock signal.
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公开(公告)号：US20200162081A1
公开(公告)日：2020-05-21
申请号：US16580161
申请日：2019-09-24
Applicant: Silicon Laboratories Inc.
Inventor： Kannanthodath V. Jayakumar , James D. Barnette
Abstract: A frequency monitoring circuit monitors a frequency offset between a first clock signal and a second clock signal. The frequency monitoring circuit includes a first moving average filter with a plurality of cascaded filter stages and a second moving average filter with a plurality of cascaded filter stages. A plurality of error detection circuits detect if differences between respective cascaded filter stages of the moving average filters exceed respective thresholds. The frequency monitoring circuit asserts a frequency error signal if any of the error detection circuits detect an error. A phase monitoring circuit asserts a phase error if a phase error is above a phase error threshold. The frequency error signal and the phase error signals are combined as a loss of lock signal.
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