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    CHIP TO CHIP TIME SYNCHRONIZATION
    11.
    发明申请
    CHIP TO CHIP TIME SYNCHRONIZATION 有权

    公开(公告)号：US20220006610A1

    公开(公告)日：2022-01-06

    申请号：US17478599

    申请日：2021-09-17

    Applicant: Space Exploration Technologies Corp.

    Inventor： Andras Tantos ,  David Francois Jacquet ,  Mario Toma

    IPC: H04L7/033

    Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal and generate a first reference time signal based on the timing signal and the reference clock signal. The IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal; the IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal. The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The second reference time signal has a finer count resolution than the first reference time signal for a same time period.

    Phase lock loop (PLL) synchronization
    12.
    发明授权
    Phase lock loop (PLL) synchronization 有权

    公开(公告)号：US11133806B1

    公开(公告)日：2021-09-28

    申请号：US16858675

    申请日：2020-04-26

    Applicant: Space Exploration Technologies Corp.

    Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

    IPC: H03L7/07 ,  H03L7/197

    Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips include respectively first, second, and third phase lock loop (PLL). The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. The first, second, and third PLLs are synchronized to each other based on the respective first, second, and third reference time signals.

    Phase lock loop (PLL) synchronization
    15.
    发明授权
    Phase lock loop (PLL) synchronization 有权

    公开(公告)号：US11329653B2

    公开(公告)日：2022-05-10

    申请号：US17401208

    申请日：2021-08-12

    Applicant: Space Exploration Technologies Corp.

    Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

    IPC: H03L7/07 ,  H03L7/197

    Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

    Chip to chip time synchronization
    16.
    发明授权
    Chip to chip time synchronization 有权

    公开(公告)号：US11153067B2

    公开(公告)日：2021-10-19

    申请号：US16858673

    申请日：2020-04-26

    Applicant: Space Exploration Technologies Corp.

    Inventor： Andras Tantos ,  David Francois Jacquet ,  Mario Toma

    IPC: H03D3/24 ,  H04L7/033

    Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. Each of the first, second, and third reference time signals is associated with a count of a number of cycles of the reference clock signal starting from a same particular cycle of the reference clock signal.

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