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公开(公告)号：US06804311B1
公开(公告)日：2004-10-12
申请号：US09526019
申请日：2000-03-15
申请人： Anand G. Dabak , Srinath Hosur , Shigenori Kinjo , Alan Gatherer
发明人： Anand G. Dabak , Srinath Hosur , Shigenori Kinjo , Alan Gatherer
IPC分类号： H04L2720
CPC分类号： H04B7/06 , H04L25/0228
摘要： A circuit for detecting a transmit diversity signal comprises a first circuit (706) arranged to receive a first synchronization code. The first synchronization code is modulated by a data signal. The first circuit produces a first output signal. A second circuit (732) is arranged to receive a plurality of predetermined signals. The second circuit produces a channel estimate. A detection circuit (710, 712) is arranged to receive the first output signal and the channel estimate. The detection circuit produces a signal corresponding to the data signal.
摘要翻译： 用于检测发射分集信号的电路包括布置成接收第一同步码的第一电路（706）。 第一同步码由数据信号调制。 第一电路产生第一输出信号。 第二电路（732）被布置成接收多个预定信号。 第二电路产生信道估计。 检测电路（710,712）被布置成接收第一输出信号和信道估计。 检测电路产生对应于数据信号的信号。
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12.发明授权Method and device for recovering synchronization on a signal transmitted to a mobile-telephone receiver 失效用于恢复发送到移动电话接收机的信号上的同步的方法和装置公开(公告)号：US06366574B1
公开(公告)日：2002-04-02
申请号：US09086689
申请日：1998-05-28
申请人： Eric Baissus , Srinath Hosur , Anand G. Dabak
发明人： Eric Baissus , Srinath Hosur , Anand G. Dabak
IPC分类号： H04J306
CPC分类号： H04L7/10 , H04L7/0334 , H04L7/041 , H04L7/046
摘要： Device for recovering synchronization on a signal transmitted to a mobile-telephone receiver, including phase-estimator means (47, 49) for the absolute value (ABS) and the sign (SIGN) of the transmitted signal, estimation processor (64) for processing the output signals of the estimators (47, 49), a sequencer (67), one input of which is connected to the output of the processor (64) and one output of which applies a mode signal to the processor, another output of the sequencer (67) being connected via a sampling-time generator (68) to the sampling-time control inputs of the estimators (47, 49).
摘要翻译： 用于恢复发送到移动电话接收机的信号的同步的装置，包括用于绝对值（ABS）的相位估计装置（47,49）和发送信号的符号（SIGN），用于处理的估计处理器 估计器（47,49）的输出信号，定序器（67），其一个输入端连接到处理器（64）的输出，其一个输出端向处理器施加模式信号，另一个输出端 定序器（67）经由采样时间发生器（68）连接到估计器（47,49）的采样时间控制输入端。
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公开(公告)号：US06345069B1
公开(公告)日：2002-02-05
申请号：US09217759
申请日：1998-12-21
IPC分类号： A61F206
CPC分类号： H04B1/70757 , H04B1/70735 , H04B1/7093 , H04B2201/70707
摘要： A circuit for detecting a signal is designed with a first serial circuit coupled to receive an input signal in response to a clock signal. The first serial circuit (121) has N taps (142-146) arranged to produce a respective plurality of first tap signals from the input signal (111). A first logic circuit (130, 132, 134, 148) is coupled to receive the plurality of first tap signals and one of N predetermined signals and the complement of N predetermined signals. The first logic circuit produces a first output signal (150) in response to the clock signal, the plurality of first tap signals and the one of N predetermined signals and the complement of N predetermined signals. A second serial circuit coupled to receive the first output signal. The second serial circuit has M taps (150, 172-184) arranged to produce a respective plurality of second tap signals from the first output signal, wherein a ratio of N/M is no greater than four. A second logic circuit (186) is coupled to receive one of a true and a complement of each of the plurality of second tap signals. The second logic circuit produces a second output signal (188) in response to the one of a true and a complement of each of the plurality of second tap signals.
摘要翻译： 用于检测信号的电路被设计成具有耦合以响应于时钟信号接收输入信号的第一串行电路。 第一串行电路（121）具有N个抽头（142-146），用于从输入信号（111）产生相应的多个第一抽头信号。 第一逻辑电路（130,132,134,148）被耦合以接收多个第一抽头信号以及N个预定信号中的一个以及N个预定信号的互补。 第一逻辑电路响应于时钟信号，多个第一抽头信号和N个预定信号中的一个以及N个预定信号的互补产生第一输出信号（150）。 耦合以接收第一输出信号的第二串行电路。 所述第二串行电路具有配置成从所述第一输出信号产生相应的多个第二抽头信号的M个抽头（150,172-184），其中N / M的比率不大于4。 第二逻辑电路（186）被耦合以接收多个第二抽头信号中的每一个的真实和补码中的一个。 所述第二逻辑电路响应于所述多个第二抽头信号中的每一个的真和互补中的一个产生第二输出信号（188）。
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公开(公告)号：US06166622A
公开(公告)日：2000-12-26
申请号：US181109
申请日：1998-10-28
摘要： A communication circuit is designed with a processing circuit (11) coupled to receive a plurality of first control signals (402, 408) from a source external to the communication circuit. The processing circuit produces a second control signal (432, 434) and a second power control (422, 436) signal during each of a plurality of predetermined time periods. The second power control signal is determined by a corresponding first control signal from said plurality of first control signals. The second power control signal is produced proximate the second control signal. A serial circuit is coupled to receive the second control signal and the second power control signal during a respective predetermined time period. The serial circuit produces the second control signal proximate the second power control signal.
摘要翻译： 通信电路被设计成具有耦合以从通信电路外部的源接收多个第一控制信号（402,408）的处理电路（11）。 处理电路在多个预定时间段的每一个期间产生第二控制信号（432,434）和第二功率控制（422,436）信号。 第二功率控制信号由来自所述多个第一控制信号的对应的第一控制信号确定。 在第二控制信号附近产生第二功率控制信号。 串联电路被耦合以在相应的预定时间段期间接收第二控制信号和第二功率控制信号。 串行电路产生靠近第二功率控制信号的第二控制信号。
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公开(公告)号：US08923362B2
公开(公告)日：2014-12-30
申请号：US13403201
申请日：2012-02-23
IPC分类号： H04B1/69 , H04B1/707 , H04B1/713 , H04B1/7083 , H04B1/7073 , H04J13/00 , H04J13/12
CPC分类号： H04B1/7083 , H04B1/70735 , H04J13/00 , H04J13/12
摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.
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16.发明授权公开(公告)号：US08681834B2
公开(公告)日：2014-03-25
申请号：US13403236
申请日：2012-02-23
CPC分类号： H04B1/7083 , H04B1/70735 , H04J13/00 , H04J13/12
摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.
摘要翻译： 无线通信系统。 该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。 多个帧中的每一个包括主同步码（PCS）和第二同步码（SSC）。 编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。 编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。 第二序列从多个序列中选择。 多个序列中的每一个相对于所有其他序列是正交的。 第三个序列是来自第一个序列的比特的子集。
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17.发明授权Primary and secondary synchronization codes from first, second, third sequences 有权来自第一，第二和第三序列的主和次同步码公开(公告)号：US08144747B2
公开(公告)日：2012-03-27
申请号：US12949413
申请日：2010-11-18
CPC分类号： H04B1/7083 , H04B1/70735 , H04J13/00 , H04J13/12
摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.
摘要翻译： 无线通信系统。 该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。 多个帧中的每一个包括主同步码（PCS）和辅同步码（SSC）。 编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。 编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。 第二序列从多个序列中选择。 多个序列中的每一个相对于多个序列中的所有其他序列是正交的。 第三序列包括来自第一序列的比特的子集。
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18.再颁专利Wireless system with transmitter having multiple transmit antennas and combining open loop and closed loop transmit diversities 有权具有发射机的无线系统具有多个发射天线并组合开环和闭环发射分集公开(公告)号：USRE42681E1
公开(公告)日：2011-09-06
申请号：US11124595
申请日：2005-05-05
申请人： Anand G. Dabak , Srinath Hosur
发明人： Anand G. Dabak , Srinath Hosur
CPC分类号： H04B7/0634 , H04B7/061 , H04B7/0669 , H04B7/0673 , H04L1/0618
摘要： A wireless communication system (40). The system comprises transmitter circuitry (42) comprising encoder circuitry (44) for receiving a plurality of symbols (Si). The system further comprises a plurality of antennas (AT1-AT4) coupled to the transmitter circuitry and for transmitting signals from the transmitter circuitry to a receiver (UST), wherein the signals are responsive to the plurality of symbols. Further, the encoder circuitry is for applying open loop diversity and closed loop diversity to the plurality of symbols to form the signals.
摘要翻译： 一种无线通信系统（40）。 该系统包括发射机电路（42），包括用于接收多个符号（Si）的编码器电路（44）。 该系统还包括耦合到发射机电路的多个天线（AT1-AT4），并用于将信号从发射机电路传输到接收机（UST），其中信号响应于多个符号。 此外，编码器电路用于向多个符号施加开环分集和闭环分集以形成信号。
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公开(公告)号：US20080273497A1
公开(公告)日：2008-11-06
申请号：US11800703
申请日：2007-05-04
申请人： Xiaolin Lu , Rao Venkatasadasiva , Zigang Yang , Anand G. Dabak , Srinath Hosur , Badri Varadarajan , Susan Yim
发明人： Xiaolin Lu , Rao Venkatasadasiva , Zigang Yang , Anand G. Dabak , Srinath Hosur , Badri Varadarajan , Susan Yim
IPC分类号： H04Q7/00
摘要： A method of wireless handover in a broadcast network (FIGS. 5 and 8) is disclosed. A wireless receiver (FIG. 4) receives a first signal (N) from a first transmitter (f1). The receiver measures a signal strength (RSSI) of the first signal. The strength of the first signal is compared to a first threshold (T0). The receiver receives a second signal (N+3) from a second transmitter (f3) in response to the step of comparing. The first and the second signals are sent to an application processor (120). The wireless receiver continues to receive the first and second signals until the application processor terminates receiving one of the first and second signals.
摘要翻译： 公开了广播网络中的无线切换的方法（图5和图8）。 无线接收器（图4）从第一发射机（f 1> 1）接收第一信号（N）。 接收机测量第一信号的信号强度（RSSI）。 将第一信号的强度与第一阈值（T 0> 0）进行比较。 响应于比较步骤，接收机从第二发射机（f 3> 3）接收第二信号（N + 3）。 第一和第二信号被发送到应用处理器（120）。 无线接收机继续接收第一和第二信号，直到应用处理器终止接收第一和第二信号之一。
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20.发明授权Maximum likelihood timing synchronizers for sampled PSK burst TDMA system 有权采样PSK突发TDMA系统的最大似然定时同步器公开(公告)号：US07003016B1
公开(公告)日：2006-02-21
申请号：US09417233
申请日：1999-10-13
申请人： Srinath Hosur , Anand G. Dabak
发明人： Srinath Hosur , Anand G. Dabak
IPC分类号： H04L27/30
CPC分类号： H04L27/2332 , H04L7/042
摘要： A method of producing a correction signal includes receiving a predetermined data sequence (500). The data sequence is sampled at predetermined times, thereby producing a sampled data sequence (522, 532). The sampled data sequence is separated into first and second sampled data sequences. A ratio is calculated (550, 558) from the first and second sampled data sequences. A correction signal is produced (556, 564) in response to the ratio.
摘要翻译： 产生校正信号的方法包括接收预定的数据序列（500）。 在预定时间采样数据序列，从而产生采样数据序列（522,532）。 采样数据序列被分成第一和第二采样数据序列。 从第一和第二采样数据序列计算一个比率（550,558）。 根据该比率产生校正信号（556,544）。
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