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公开(公告)号：US20180349241A1
公开(公告)日：2018-12-06
申请号：US16102193
申请日：2018-08-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shrey Bhatia , Christian Wiencke , Armin Stingl , Ralph Ledwa , Wolfgang Lutsch
IPC: G06F11/273 , G06F11/30 , G06F11/36 , G06F11/34
CPC classification number: G06F11/273 , G06F11/3024 , G06F11/3089 , G06F11/348 , G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F11/3664 , Y02D10/34
Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.
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公开(公告)号：US20180349097A1
公开(公告)日：2018-12-06
申请号：US16056115
申请日：2018-08-06
Applicant: Texas Instruments Incorporated
Inventor： Christian Wiencke , Armin Stingl
CPC classification number: G06F7/44 , G06F7/42 , G06F7/5324
Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.
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公开(公告)号：US20240012727A1
公开(公告)日：2024-01-11
申请号：US18474690
申请日：2023-09-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shrey Bhatia , Christian Wiencke , Armin Stingl , Ralph Ledwa , Wolfgang Lutsch
IPC: G06F11/273 , G06F11/36 , G06F11/34 , G06F11/30 , G06F11/26
CPC classification number: G06F11/273 , G06F11/3636 , G06F11/3664 , G06F11/3648 , G06F11/348 , G06F11/3656 , G06F11/3024 , G06F11/3089 , G06F11/26
Abstract: A processor includes execution circuitry, within an execution power domain, to process an instruction; and a debug system, within a separate debug power domain, to selectively operate to perform debugging operations on the processor. The processor further includes power control circuitry coupled to the debug system; and detection circuitry coupled to the power control circuitry. The power control circuitry causes power to be supplied to the debug system when the detection circuitry indicates that a debug tool is coupled to the processor, and disables power supply to the debug system when the detection circuitry indicates that the debug tool is not coupled to the processor.
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公开(公告)号：US10042605B2
公开(公告)日：2018-08-07
申请号：US15132280
申请日：2016-04-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Christian Wiencke , Armin Stingl
Abstract: A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.
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