公开(公告)号：US10891207B2

公开(公告)日：2021-01-12

申请号：US16102193

申请日：2018-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US10049025B2

公开(公告)日：2018-08-14

申请号：US15200900

申请日：2016-07-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US11593241B2

公开(公告)日：2023-02-28

申请号：US17146584

申请日：2021-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US11513804B2

公开(公告)日：2022-11-29

申请号：US17029299

申请日：2020-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Markus Koesler ,  Johann Zipperer ,  Christian Wiencke ,  Wolfgang Lutsch

IPC: G06F11/36 ,  G06F9/38 ,  G06F11/267 ,  G06F9/30

Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

公开(公告)号：US11803455B2

公开(公告)日：2023-10-31

申请号：US18175607

申请日：2023-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

CPC classification number: G06F11/273 ,  G06F11/26 ,  G06F11/3024 ,  G06F11/3089 ,  G06F11/348 ,  G06F11/3636 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/3664

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US20230205656A1

公开(公告)日：2023-06-29

申请号：US18175607

申请日：2023-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

CPC classification number: G06F11/273 ,  G06F11/3636 ,  G06F11/3664 ,  G06F11/3648 ,  G06F11/348 ,  G06F11/3656 ,  G06F11/3024 ,  G06F11/3089 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US20210133065A1

公开(公告)日：2021-05-06

申请号：US17146584

申请日：2021-01-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US20210004236A1

公开(公告)日：2021-01-07

申请号：US17029299

申请日：2020-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Markus Koesler ,  Johann Zipperer ,  Christian Wiencke ,  Wolfgang Lutsch

IPC: G06F9/38 ,  G06F11/36 ,  G06F11/267 ,  G06F9/30

Abstract: A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.

公开(公告)号：US20180349241A1

公开(公告)日：2018-12-06

申请号：US16102193

申请日：2018-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/273 ,  G06F11/30 ,  G06F11/36 ,  G06F11/34

CPC classification number: G06F11/273 ,  G06F11/3024 ,  G06F11/3089 ,  G06F11/348 ,  G06F11/3636 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  Y02D10/34

Abstract: A processor includes an execution pipeline that includes a plurality of execution stages, execution pipeline control logic, and a debug system. The execution pipeline control logic is configured to control flow of an instruction through the execution stages. The debug system includes a debug pipeline and debug pipeline control logic. The debug pipeline includes a plurality of debug stages. Each debug pipeline stage corresponds to an execution pipeline stage, and the total number of debug stages corresponds to the total number of execution stages. The debug pipeline control logic is coupled to the execution pipeline control logic. The debug pipeline control logic is configured to control flow through the debug stages of debug information associated with the instruction, and to advance the debug information into a next of the debug stages in correspondence with the execution pipeline control logic advancing the instruction into a corresponding stage of the execution pipeline.

公开(公告)号：US20240012727A1

公开(公告)日：2024-01-11

申请号：US18474690

申请日：2023-09-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shrey Bhatia ,  Christian Wiencke ,  Armin Stingl ,  Ralph Ledwa ,  Wolfgang Lutsch

IPC: G06F11/273 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30 ,  G06F11/26

CPC classification number: G06F11/273 ,  G06F11/3636 ,  G06F11/3664 ,  G06F11/3648 ,  G06F11/348 ,  G06F11/3656 ,  G06F11/3024 ,  G06F11/3089 ,  G06F11/26

Abstract: A processor includes execution circuitry, within an execution power domain, to process an instruction; and a debug system, within a separate debug power domain, to selectively operate to perform debugging operations on the processor. The processor further includes power control circuitry coupled to the debug system; and detection circuitry coupled to the power control circuitry. The power control circuitry causes power to be supplied to the debug system when the detection circuitry indicates that a debug tool is coupled to the processor, and disables power supply to the debug system when the detection circuitry indicates that the debug tool is not coupled to the processor.