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公开(公告)号:US20190052262A1
公开(公告)日:2019-02-14
申请号:US16161124
申请日:2018-10-16
Applicant: Texas Instruments Incorporated
Inventor: Giacomo Calabrese , Maurizio Granato , Giovanni Frattini
IPC: H03K17/691 , H03K5/08 , H03K19/00
Abstract: Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage.
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公开(公告)号:US20180309443A1
公开(公告)日:2018-10-25
申请号:US15492256
申请日:2017-04-20
Inventor: Giacomo Calabrese , Maurizio Granato , Giovanni Frattini
IPC: H03K17/691 , H03K5/08 , H03K19/00
CPC classification number: H03K17/691 , H03K5/08 , H03K19/0005
Abstract: Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage.
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公开(公告)号:US20160214140A1
公开(公告)日:2016-07-28
申请号:US15089752
申请日:2016-04-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Maurizio Granato , Giovanni Frattini , Roberto Massolini
IPC: B06B1/02
CPC classification number: B06B1/0284 , B06B1/0292 , H04R1/00 , H04R3/06 , H04R2217/03
Abstract: A transducer has an input and produces a mechanical output, wherein the magnitude of the mechanical output of the transducer is dependent on the frequency and magnitude of current at the input. A driver for the transducer includes a device having a transfer function associated with the device, the device having a device input and a device output, the device output being connectable to the input of the transducer and the device input being connectable to a power source. The device attenuates the current output at a frequency that causes a peak in the magnitude of the mechanical output of the transducer.
Abstract translation: 换能器具有输入并产生机械输出,其中换能器的机械输出的大小取决于输入端的电流的频率和幅度。 用于换能器的驱动器包括具有与装置相关联的传递功能的装置,所述装置具有装置输入和装置输出,所述装置输出可连接到所述换能器的输入端,所述装置输入可连接到电源。 该器件以导致换能器的机械输出大小的峰值的频率衰减电流输出。
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公开(公告)号:US09338533B2
公开(公告)日:2016-05-10
申请号:US14204280
申请日:2014-03-11
Applicant: Texas Instruments Incorporated
Inventor: Maurizio Granato , Giovanni Frattini , Roberto Giampiero Massolini
CPC classification number: B06B1/0284 , B06B1/0292 , H04R1/00 , H04R3/06 , H04R2217/03
Abstract: A transducer has an input and produces a mechanical output, wherein the magnitude of the mechanical output of the transducer is dependent on the frequency and magnitude of current at the input. A driver for the transducer includes a device having a transfer function associated with the device, the device having a device input and a device output, the device output being connectable to the input of the transducer and the device input being connectable to a power source. The device attenuates the current output at a frequency that causes a peak in the magnitude of the mechanical output of the transducer.
Abstract translation: 换能器具有输入并产生机械输出,其中换能器的机械输出的大小取决于输入端的电流的频率和幅度。 用于换能器的驱动器包括具有与装置相关联的传递功能的装置,所述装置具有装置输入和装置输出,所述装置输出可连接到所述换能器的输入端,所述装置输入可连接到电源。 该器件以导致换能器的机械输出大小的峰值的频率衰减电流输出。
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15.
公开(公告)号:US10454369B2
公开(公告)日:2019-10-22
申请号:US15591107
申请日:2017-05-10
Applicant: Texas Instruments Incorporated
Inventor: Filip Savic , Giacomo Calabrese , Giovanni Frattini
Abstract: A switched voltage converter may be controlled with load current feedforward control loop in addition to an output voltage feedback loop. The converter includes a first switch device that is controlled to open and close at a selected switching rate with a selected duty cycle. The first switch device is coupled in series with an inductor and conducts current through the inductor while the first switch is closed. A second switch device conducts current from the inductor to an output capacitor and to load while the first switch is open to produce an output voltage and a resulting load current through the load. The load current is measured in a continuous manner and a load current feedforward control signal is generated that is representative of the load current. The switch rate and/or duty cycle of the first switch is adjusted in response to the load current feedforward control signal.
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公开(公告)号:US10432102B2
公开(公告)日:2019-10-01
申请号:US15712330
申请日:2017-09-22
Applicant: Texas Instruments Incorporated
Inventor: Pierluigi Albertini , Maurizio Granato , Giacomo Calabrese , Roberto Giampiero Massolini , Joyce Marie Mullenix , Giovanni Frattini
Abstract: Disclosed examples include isolated dual active bridge (DAB) DC to DC converters with first and second bridge circuits, a transformer with a sense coil, and a secondary side control circuit to provide secondary side switching control signals to regulate an output voltage or current signal by controlling a phase shift angle between switching transitions of the secondary side switching control signals and switching transitions of a secondary side clock signal, where the secondary side control circuit includes a clock recovery circuit to synchronize the secondary side clock signal to transitions in a sense coil voltage signal of the sense coil.
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17.
公开(公告)号:US20190229637A1
公开(公告)日:2019-07-25
申请号:US16367691
申请日:2019-03-28
Applicant: Texas Instruments Incorporated
Inventor: Pierluigi Albertini , Maurizio Granato , Giacomo Calabrese , Roberto Giampiero Massolini , Joyce Marie Mullenix , Giovanni Frattini
Abstract: Disclosed examples include isolated dual active bridge (DAB) DC to DC converters with first and second bridge circuits, a transformer with a sense coil, and a secondary side control circuit to provide secondary side switching control signals to regulate an output voltage or current signal by controlling a phase shift angle between switching transitions of the secondary side switching control signals and switching transitions of a secondary side clock signal, where the secondary side control circuit includes a clock recovery circuit to synchronize the secondary side clock signal to transitions in a sense coil voltage signal of the sense coil.
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公开(公告)号:US20190097544A1
公开(公告)日:2019-03-28
申请号:US15712330
申请日:2017-09-22
Applicant: Texas Instruments Incorporated
Inventor: Pierluigi Albertini , Maurizio Granato , Giacomo Calabrese , Roberto Giampiero Massolini , Joyce Marie Mullenix , Giovanni Frattini
CPC classification number: H02M3/33592 , H02M3/33584 , H02M2001/0003 , H03L7/0807
Abstract: Disclosed examples include isolated dual active bridge (DAB) DC to DC converters with first and second bridge circuits, a transformer with a sense coil, and a secondary side control circuit to provide secondary side switching control signals to regulate an output voltage or current signal by controlling a phase shift angle between switching transitions of the secondary side switching control signals and switching transitions of a secondary side clock signal, where the secondary side control circuit includes a clock recovery circuit to synchronize the secondary side clock signal to transitions in a sense coil voltage signal of the sense coil.
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公开(公告)号:US10135439B2
公开(公告)日:2018-11-20
申请号:US15492256
申请日:2017-04-20
Applicant: Texas Instruments Incorporated
Inventor: Giacomo Calabrese , Maurizio Granato , Giovanni Frattini
IPC: H03K5/08 , H03K17/691 , H03K19/00
Abstract: Disclosed examples include isolated load switch driver circuits to drive a load, including an impedance circuit that receives a digital input voltage signal from a signal source, and selectively allows a current signal to flow from the signal source to charge a buffer capacitor. An impedance control circuit controls the impedance circuit to limit the current signal in response to the buffer capacitor reaching a first threshold voltage, and an output circuit provides an output isolated from the digital input voltage signal to switch the load. A signaling circuit selectively enables the output circuit to draw power from the buffer capacitor in response to the voltage of the buffer capacitor reaching the first threshold voltage.
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公开(公告)号:US20180152109A1
公开(公告)日:2018-05-31
申请号:US15363188
申请日:2016-11-29
Applicant: Texas Instruments Incorporated
Inventor: Shailendra Kumar Baranwal , Maurizio Granato , Giovanni Frattini
CPC classification number: H02M3/33592 , H02M1/08 , H02M3/33553 , H02M2001/0058
Abstract: An electronic device, which includes an H-bridge circuit and a miniaturized transformer that is coupled to operate at VHF frequency, and a driver circuit for an n-type power transistor of the H-bridge circuit are disclosed. The driver circuit includes a first p-type transistor and an n-type transistor coupled between an upper rail and a lower rail, with an output taken between the drains of the first p-type transistor and the n-type transistor being coupled to a gate of the n-type power transistor. The driver circuit also includes a sample-and-hold capacitor coupled to capture a drain voltage for the first n-type power transistor on a first edge of a control signal for the first n-type power transistor and a comparator coupled to compare the captured drain voltage to a lower rail on a given edge of a clock signal and to provide a comparator value. The driver circuit also includes an up/down counter, which is coupled to receive the comparator value, to adjust a counter value responsive to receiving the comparator value and to output the counter value, and a first timing circuit that is coupled to receive the counter value and to send an adjustable pulse towards a gate of the first p-type transistor and a gate of the n-type transistor.
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