公开(公告)号：US20230384854A1

公开(公告)日：2023-11-30

申请号：US18450079

申请日：2023-08-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F1/3234 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0848 ,  G06F2212/1028 ,  Y02D10/00 ,  G06F2212/282 ,  G06F2212/283

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

公开(公告)号：US11775046B2

公开(公告)日：2023-10-03

申请号：US17541776

申请日：2021-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F1/3234 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F12/0811 ,  G06F12/0848 ,  G06F12/0895 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/283 ,  Y02D10/00

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

公开(公告)号：US11221665B2

公开(公告)日：2022-01-11

申请号：US16933407

申请日：2020-07-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F1/3234 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0846

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

公开(公告)号：US10725527B2

公开(公告)日：2020-07-28

申请号：US16253363

申请日：2019-01-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F1/3234 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0846

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

公开(公告)号：US09811148B2

公开(公告)日：2017-11-07

申请号：US15431922

申请日：2017-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F1/32 ,  G06F12/08 ,  G06F12/0846 ,  G06F12/0811

CPC classification number: G06F1/3275 ,  G06F12/0811 ,  G06F12/0848 ,  G06F12/0895 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/283 ,  Y02D10/13

Abstract: The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

公开(公告)号：US20170153691A1

公开(公告)日：2017-06-01

申请号：US15431922

申请日：2017-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F1/32 ,  G06F12/0811 ,  G06F12/0846

CPC classification number: G06F1/3275 ,  G06F12/0811 ,  G06F12/0848 ,  G06F12/0895 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/283 ,  Y02D10/13

Abstract: The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.