公开(公告)号：US09347991B1

公开(公告)日：2016-05-24

申请号：US14539555

申请日：2014-11-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mudasir Shafat Kawoosa ,  Rajesh Kumar Mittal ,  Sreenath Narayanan Potty

IPC: G01R31/28 ,  G01R31/3177 ,  G11C29/12

CPC classification number: G11C29/12 ,  G01R31/28 ,  G01R31/318563 ,  G11C29/32

Abstract: Systems and methods for enabling scan testing of device-under-test (DUT) are disclosed. In an embodiment, a test system for scan testing the DUT, including P scan input ports and Q scan output ports, includes tester and adapter module. Tester operates at clock frequency F1 and includes M tester Input/Output (I/O) ports for providing M scan inputs and N tester I/O ports for receiving N scan outputs at F1. Adapter module is coupled to tester and configured to receive M scan inputs at F1 and, in response, provide P scan inputs at clock frequency F2 to P scan input ports, and to receive Q scan outputs at F2 from Q scan output ports and, in response, provide N scan outputs at F1 to N tester I/O ports, where ratio of M to P equals ratio of N to Q, and where each of M, N, P and Q are positive integers.

Abstract translation: 公开了用于启用被测器件（DUT）的扫描测试的系统和方法。 在一个实施例中，用于扫描测试DUT的测试系统，包括P扫描输入端口和Q扫描输出端口，包括测试器和适配器模块。 测试仪以时钟频率F1工作，并包括M测试仪输入/输出（I / O）端口，用于提供M扫描输入和N个测试仪I / O端口，用于在F1接收N个扫描输出。 适配器模块耦合到测试器，并配置为在F1接收M个扫描输入，作为响应，在时钟频率F2提供P扫描输入到P扫描输入端口，并从Q扫描输出端口接收F2的Q扫描输出，并在 响应，在F1到N测试仪I / O端口提供N个扫描输出，其中M与P的比值等于N与Q的比率，并且其中M，N，P和Q中的每一个是正整数。

公开(公告)号：US11821945B2

公开(公告)日：2023-11-21

申请号：US17217391

申请日：2021-03-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rajesh Kumar Mittal ,  Rajat Mehrotra

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/31713 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318572

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

公开(公告)号：US10088525B2

公开(公告)日：2018-10-02

申请号：US15042130

申请日：2016-02-11

Applicant: Texas Instruments Incorporated

Inventor： Mudasir Shafat Kawoosa ,  Rajesh Kumar Mittal

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

公开(公告)号：US20170234925A1

公开(公告)日：2017-08-17

申请号：US15042130

申请日：2016-02-11

Applicant: Texas Instruments Incorporated

Inventor： Mudasir Shafat Kawoosa ,  Rajesh Kumar Mittal

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/318572 ,  G01R31/318594

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

公开(公告)号：US09581645B2

公开(公告)日：2017-02-28

申请号：US14179046

申请日：2014-02-12

Applicant: Texas Instruments Incorporated

Inventor： Adesh Sontakke ,  Rajesh Kumar Mittal ,  Rubin A. Parekhji ,  Upendra Narayan Tripathi

IPC: G01R31/319 ,  G01R31/14 ,  G01R31/317

CPC classification number: G01R31/31917 ,  G01R31/31716 ,  G01R31/31724

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with the storage circuit (110) and with the functional circuit modules (IP.i. The test controller (140, 150) is operable to dynamically schedule and trigger the tests in those sets, which promotes concurrent execution of tests in the functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Abstract translation: 可测试的集成电路芯片（80,100）包括具有模块（IP.i）的功能电路（80），存储电路（110），其可操作以保持表示兼容兼容的兼容测试集合的表，以及on 芯片测试控制器（140,150）与存储电路（110）和功能电路模块（IP.i）耦合。测试控制器（140,150）可操作以动态地调度和触发那些组中的测试，其中 促进并行执行功能电路模块（IP.i）中的测试，公开了其他电路，无线芯片，系统以及操作过程和制造过程。

公开(公告)号：US09239360B2

公开(公告)日：2016-01-19

申请号：US14165846

申请日：2014-01-28

Applicant: Texas Instruments Incorporated

Inventor： Rajesh Kumar Mittal ,  Charles Kurian ,  Sumanth Reddy Poddutur

IPC: G01R31/3185

CPC classification number: G01R31/318552 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318555 ,  G01R31/318563 ,  G01R31/31858

Abstract: A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that receives a scan data input. A flip-flop is coupled to an output of the first multiplexer and generates a scan pattern. An inverter generates an inverted feedback signal in response to the scan pattern. The inverted feedback signal is provided to the first multiplexer. A plurality of logic circuits is connected in a scan chain and generates a logic output in response to the scan pattern. A bypass multiplexer is coupled to the plurality of logic circuits. The bypass multiplexer generates a scan output in response to the logic output, the scan data input and a segment bypass input.

Abstract translation: 提供了一种有助于更快地诊断连接在扫描链中的多个逻辑电路的电路。 电路包括接收扫描数据输入的第一多路复用器。 触发器耦合到第一多路复用器的输出并产生扫描模式。 逆变器响应于扫描模式产生反相反馈信号。 反向反馈信号被提供给第一多路复用器。 多个逻辑电路连接在扫描链中并且响应于扫描图案而产生逻辑输出。 旁路多路复用器耦合到多个逻辑电路。 旁路多路复用器响应于逻辑输出，扫描数据输入和段旁路输入产生扫描输出。

公开(公告)号：US20150212150A1

公开(公告)日：2015-07-30

申请号：US14165846

申请日：2014-01-28

Applicant: Texas Instruments Incorporated

Inventor： Rajesh Kumar Mittal ,  Charles Kurian ,  Sumanth Reddy Poddutur

IPC: G01R31/3177

CPC classification number: G01R31/318552 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318555 ,  G01R31/318563 ,  G01R31/31858

Abstract: A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that receives a scan data input. A flip-flop is coupled to an output of the first multiplexer and generates a scan pattern. An inverter generates an inverted feedback signal in response to the scan pattern. The inverted feedback signal is provided to the first multiplexer. A plurality of logic circuits is connected in a scan chain and generates a logic output in response to the scan pattern. A bypass multiplexer is coupled to the plurality of logic circuits. The bypass multiplexer generates a scan output in response to the logic output, the scan data input and a segment bypass input.

Abstract translation: 提供了一种有助于更快地诊断连接在扫描链中的多个逻辑电路的电路。 电路包括接收扫描数据输入的第一多路复用器。 触发器耦合到第一多路复用器的输出并产生扫描模式。 逆变器响应于扫描模式产生反相反馈信号。 反向反馈信号被提供给第一多路复用器。 多个逻辑电路连接在扫描链中并且响应于扫描图案而产生逻辑输出。 旁路多路复用器耦合到多个逻辑电路。 旁路多路复用器响应于逻辑输出，扫描数据输入和段旁路输入产生扫描输出。