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公开(公告)号：US11821945B2
公开(公告)日：2023-11-21
申请号：US17217391
申请日：2021-03-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prakash Narayanan , Rajesh Kumar Mittal , Rajat Mehrotra
IPC: G01R31/317 , G01R31/3185 , G01R31/3177
CPC classification number: G01R31/31713 , G01R31/3177 , G01R31/318536 , G01R31/318572
Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.
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公开(公告)号：US20170157524A1
公开(公告)日：2017-06-08
申请号：US15434717
申请日：2017-02-16
Applicant: Texas Instruments Incorporated
Inventor： Prakash Narayanan , Nikita Naresh , Vaskar Sarkar , Rajat Mehrotra
IPC: G11C29/00
CPC classification number: G11C29/12 , G11C29/38 , G11C29/40 , G11C2029/0401 , G11C2029/2602
Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
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公开(公告)号：US20180174663A1
公开(公告)日：2018-06-21
申请号：US15896817
申请日：2018-02-14
Applicant: Texas Instruments Incorporated
Inventor： Prakash Narayanan , Nikita Naresh , Vaskar Sarkar , Rajat Mehrotra
IPC: G11C29/12
CPC classification number: G11C29/12 , G11C29/38 , G11C29/40 , G11C2029/0401 , G11C2029/2602
Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
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公开(公告)号：US09899103B2
公开(公告)日：2018-02-20
申请号：US15434717
申请日：2017-02-16
Applicant: Texas Instruments Incorporated
Inventor： Prakash Narayanan , Nikita Naresh , Vaskar Sarkar , Rajat Mehrotra
CPC classification number: G11C29/12 , G11C29/38 , G11C29/40 , G11C2029/0401 , G11C2029/2602
Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
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公开(公告)号：US20180045778A1
公开(公告)日：2018-02-15
申请号：US15722975
申请日：2017-10-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prakash Narayanan , Rajesh Mittal , Rajat Mehrotra
IPC: G01R31/317 , G01R31/3185 , G01R31/3177
CPC classification number: G01R31/31713 , G01R31/3177 , G01R31/318536 , G01R31/318572
Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.
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Patent Agency Ranking
公开(公告)号：US20210215757A1
公开(公告)日：2021-07-15
申请号：US17217391
申请日：2021-03-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prakash Narayanan , Rajesh Kumar Mittal , Rajat Mehrotra
IPC: G01R31/317 , G01R31/3177 , G01R31/3185
Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.
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公开(公告)号：US10983161B2
公开(公告)日：2021-04-20
申请号：US16380182
申请日：2019-04-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prakash Narayanan , Rajesh Kumar Mittal , Rajat Mehrotra
IPC: G01R31/317 , G01R31/3185 , G01R31/3177
Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.
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公开(公告)号：US10460821B2
公开(公告)日：2019-10-29
申请号：US15896817
申请日：2018-02-14
Applicant: Texas Instruments Incorporated
Inventor： Prakash Narayanan , Nikita Naresh , Vaskar Sarkar , Rajat Mehrotra
Abstract: A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
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公开(公告)号：US20150325308A1
公开(公告)日：2015-11-12
申请号：US14490170
申请日：2014-09-18
Applicant: Texas Instruments Incorporated
Inventor： Rajat Mehrotra , Rubin Ajit Parekhji , Maheedhar Jalasutram , Charu Shrimali
CPC classification number: G11C16/3422 , G11C16/00 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , G11C29/12 , G11C29/26 , G11C29/4401 , G11C2029/2602
Abstract: An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.
Abstract translation: 用于一组闪速存储器组装置的并发测试的装置包括耦合到测试控制器的存储器数据路径（MDP）模块。 MDP模块包括测试控制模块，其被配置为生成并发控制信号，其配置要同时测试的闪存组集合; 以及一组比较器，其响应于并发控制信号和来自闪存组的输入而产生第一比较器输出。 还原逻辑被配置为生成还原逻辑输出，其组合要压缩的比较器输出的状态。 控制逻辑被配置用于跨越闪存组的不同闪存位的选择性编程。 如果在任何访问中从闪存组中读取的数据不匹配，则失败标志被配置为产生输出值“0”，并且如果在任何访问中读取的数据不匹配，则输出值1 。
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公开(公告)号：US20190235020A1
公开(公告)日：2019-08-01
申请号：US16380182
申请日：2019-04-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prakash Narayanan , Rajesh Kumar Mittal , Rajat Mehrotra
IPC: G01R31/317 , G01R31/3177 , G01R31/3185
CPC classification number: G01R31/31713 , G01R31/3177 , G01R31/318536 , G01R31/318572
Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.
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