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公开(公告)号：US20210183717A1
公开(公告)日：2021-06-17
申请号：US16859530
申请日：2020-04-27
Applicant: Texas Instruments Incorporated
Inventor： Amit Sureshkumar Nangia , Sreenivasan Kalyani Koduri , Siva Prakash Gurrum , Christopher Daniel Manack
Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.
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公开(公告)号：US09157938B2
公开(公告)日：2015-10-13
申请号：US13668586
申请日：2012-11-05
Applicant: Texas Instruments Incorporated
Inventor： Young-Joon Park , Siva Prakash Gurrum
CPC classification number: G01R19/04
Abstract: A method of computing a peak current density specification (jpeakspec) for an electrical conductor line of an integrated circuit (IC) resulting from conducting pulsed electrical current represented as a current waveform. An on-time (ton) is identified for the current waveform based on a current density being greater than or equal to (≧) a predetermined current density level. The jpeakspec is computed for the electrical conductor line using a jpeakspec modeling equation which includes the ton for the current waveform and a thermal time constant (τ) for the electrical conductor line.
Abstract translation: 计算通过表示为电流波形的脉冲电流导致的集成电路（IC）的导电线的峰值电流密度规格（jpeakspec）的方法。 基于大于或等于（≥）预定电流密度级的电流密度，为当前波形识别导通时间（ton）。 使用jpeakspec建模方程计算电导体线的jpeakspec，该方程包括电流波形的ton和电导体线的热时间常数（τ）。
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公开(公告)号：US11869820B2
公开(公告)日：2024-01-09
申请号：US17810568
申请日：2022-07-01
Applicant: Texas Instruments Incorporated
Inventor： Amit Sureshkumar Nangia , Sreenivasan Kalyani Koduri , Siva Prakash Gurrum , Christopher Daniel Manack
CPC classification number: H01L23/16 , H01L24/97 , H01L2224/73265 , H01L2924/14
Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.
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14.发明授权公开(公告)号：US11521904B2
公开(公告)日：2022-12-06
申请号：US16815130
申请日：2020-03-11
Applicant: Texas Instruments Incorporated
Inventor： Hung-Yun Lin , Siva Prakash Gurrum
IPC: H01L21/66 , H01L23/522 , H01L23/528 , H01L23/495 , H01L23/00 , G01R31/52 , G01R1/067
Abstract: An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and ≥1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.
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Patent Agency Ranking
公开(公告)号：US11387155B2
公开(公告)日：2022-07-12
申请号：US16859530
申请日：2020-04-27
Applicant: Texas Instruments Incorporated
Inventor： Amit Sureshkumar Nangia , Sreenivasan Kalyani Koduri , Siva Prakash Gurrum , Christopher Daniel Manack
Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.
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公开(公告)号：US11139178B2
公开(公告)日：2021-10-05
申请号：US16653536
申请日：2019-10-15
Applicant: Texas Instruments Incorporated
IPC: H01L21/56 , H01L23/29 , H01L23/495 , C08G59/18 , H01L23/64 , H01L23/522 , H01L23/00 , H01L23/50 , H01L23/31
Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.
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公开(公告)号：US20200243428A1
公开(公告)日：2020-07-30
申请号：US16848774
申请日：2020-04-14
Applicant: Texas Instruments Incorporated
Inventor： Siva Prakash Gurrum , Manu J. Prakuzhy , Saumya Gandhi
IPC: H01L23/495 , H01L23/00 , H01L21/56
Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.
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公开(公告)号：US20190172766A1
公开(公告)日：2019-06-06
申请号：US16249756
申请日：2019-01-16
Applicant: Texas Instruments Incorporated
Inventor： Siva Prakash Gurrum , Amit Sureshkumar Nangia
IPC: H01L23/16 , H01L23/00 , H01L23/495 , H01L23/31 , H01L23/29
Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.
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公开(公告)号：US10204842B2
公开(公告)日：2019-02-12
申请号：US15896860
申请日：2018-02-14
Applicant: Texas Instruments Incorporated
Inventor： Siva Prakash Gurrum , Amit Sureshkumar Nangia
IPC: H01L23/00 , H01L23/16 , H01L23/495
Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.
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