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公开(公告)号：US20220336304A1
公开(公告)日：2022-10-20
申请号：US17810568
申请日：2022-07-01
发明人： Amit Sureshkumar Nangia , Sreenivasan Kalyani Koduri , Siva Prakash Gurrum , Christopher Daniel Manack
摘要： An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.
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公开(公告)号：US20220230944A1
公开(公告)日：2022-07-21
申请号：US17560229
申请日：2021-12-22
IPC分类号： H01L23/498 , H01L23/00 , H01L23/31 , H01L21/48
摘要： A semiconductor package includes a base insulating layer; a semiconductor die attached to a portion of the base insulating layer; and a first continuous lead electrically connected to the semiconductor die. The first continuous lead includes a first lateral extension on a first surface of the base insulating layer, a second lateral extension on a second surface of the base insulating layer, and a connecting portion between the first lateral extension and the second lateral extension. The connecting portion penetrates through the base insulating layer.
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公开(公告)号：US11239195B2
公开(公告)日：2022-02-01
申请号：US16843580
申请日：2020-04-08
IPC分类号： H01L23/31 , H01L21/78 , H01L23/495 , H01L23/00
摘要： In some examples, a system comprises a first component having a first surface, a first set of nanoparticles coupled to the first surface, and a first set of nanowires extending from the first set of nanoparticles. The system also comprises a second component having a second surface, a second set of nanoparticles coupled to the second surface, and a second set of nanowires extending from the second set of nanoparticles. The system further includes an adhesive positioned between the first and second surfaces. The first and second sets of nanowires are positioned within the adhesive.
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公开(公告)号：US11869820B2
公开(公告)日：2024-01-09
申请号：US17810568
申请日：2022-07-01
发明人： Amit Sureshkumar Nangia , Sreenivasan Kalyani Koduri , Siva Prakash Gurrum , Christopher Daniel Manack
CPC分类号： H01L23/16 , H01L24/97 , H01L2224/73265 , H01L2924/14
摘要： An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.
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公开(公告)号：US20230352373A1
公开(公告)日：2023-11-02
申请号：US18297751
申请日：2023-04-10
IPC分类号： H01L23/495 , H01L21/56 , H01L21/48 , H01L23/31
CPC分类号： H01L23/4952 , H01L21/565 , H01L23/49575 , H01L23/49513 , H01L21/4825 , H01L23/3114 , H01L23/49527
摘要： In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.
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公开(公告)号：US11791296B2
公开(公告)日：2023-10-17
申请号：US17544888
申请日：2021-12-07
发明人： Scott Robert Summerfelt , Benjamin Stassen Cook , Ralf Jakobskrueger Muenster , Sreenivasan Kalyani Koduri
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L2224/13005 , H01L2224/13023 , H01L2224/13026 , H01L2224/13078 , H01L2224/279 , H01L2224/29078 , H01L2224/3207 , H01L2224/83895 , H01L2224/83896
摘要： In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.
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公开(公告)号：US20230163050A1
公开(公告)日：2023-05-25
申请号：US18152733
申请日：2023-01-10
IPC分类号： H01L23/495 , H01L23/31 , H01L21/56 , H05K1/18 , H01L23/552 , H05K3/34
CPC分类号： H01L23/49558 , H01L23/3135 , H01L23/49555 , H01L21/56 , H05K1/181 , H01L23/552 , H05K3/3426 , H05K2201/10931 , H01L23/49586 , H01L21/4842
摘要： In examples, a semiconductor device comprises a semiconductor die, an opaque mold compound housing covering the semiconductor die, a conductive terminal extending from the mold compound housing, and an insulative coat covering the mold compound housing and at least a portion of the conductive terminal.
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公开(公告)号：US11387155B2
公开(公告)日：2022-07-12
申请号：US16859530
申请日：2020-04-27
发明人： Amit Sureshkumar Nangia , Sreenivasan Kalyani Koduri , Siva Prakash Gurrum , Christopher Daniel Manack
摘要： An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.
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公开(公告)号：US11972994B2
公开(公告)日：2024-04-30
申请号：US18299293
申请日：2023-04-12
CPC分类号： H01L23/31 , H01L21/565 , H01L23/142 , H01L23/293 , H01L23/564 , H01L25/0655
摘要： In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.
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公开(公告)号：US11791248B2
公开(公告)日：2023-10-17
申请号：US18152733
申请日：2023-01-10
IPC分类号： H01L21/48 , H01L23/495 , H01L23/31 , H01L21/56 , H05K1/18 , H01L23/552 , H05K3/34
CPC分类号： H01L21/4821 , H01L21/56 , H01L23/3135 , H01L23/49555 , H01L23/49558 , H01L23/552 , H05K1/181 , H05K3/3426 , H01L21/4842 , H01L23/49586 , H05K2201/10931
摘要： In examples, a semiconductor device comprises a semiconductor die, an opaque mold compound housing covering the semiconductor die, a conductive terminal extending from the mold compound housing, and an insulative coat covering the mold compound housing and at least a portion of the conductive terminal.
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