公开(公告)号：US20240355763A1

公开(公告)日：2024-10-24

申请号：US18761075

申请日：2024-07-01

申请人： Advanced Semiconductor Engineering, Inc.

发明人： En Hao HSU ,  Kuo Hwa TZENG ,  Chia-Pin CHEN ,  Chi Long TSAI

IPC分类号： H01L23/00 ,  H01L23/16 ,  H01L23/31

CPC分类号： H01L23/562 ,  H01L23/16 ,  H01L23/3107 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/022 ,  H01L2224/02377 ,  H01L2224/13018

摘要： An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.

公开(公告)号：US12100641B2

公开(公告)日：2024-09-24

申请号：US18223221

申请日：2023-07-18

申请人： SILICONWARE PRECISION INDUSTRIES CO., LTD.

发明人： Chih-Hsien Chiu ,  Siang-Yu Lin ,  Wen-Jung Tsai ,  Chia-Yang Chen ,  Chien-Cheng Lin

IPC分类号： H01L23/42 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367

CPC分类号： H01L23/42 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/367

摘要： An electronic package is provided, which includes a plurality of electronic components encapsulated by an encapsulation layer. A spacer is defined in the encapsulation layer and located between at least two adjacent electronic components of the plurality of electronic components, and a recess is formed in the spacer and used as a thermal insulation area. With the design of the thermal insulation area, the plurality of electronic components can be effectively thermally insulated from one another to prevent heat generated by one electronic component of high power from being conducted to another electronic component of low power that would thermally affect the operation of the low-power electronic component. A method for manufacturing the electronic package is also provided.

公开(公告)号：US20240312930A1

公开(公告)日：2024-09-19

申请号：US18673328

申请日：2024-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kai-Ming Ching ,  Shu-Shen Yeh ,  Chien-Hung Chen ,  Hui-Chang Yu ,  Yu-Min Cheng

IPC分类号： H01L23/552 ,  H01L21/50 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

CPC分类号： H01L23/552 ,  H01L21/50 ,  H01L23/16 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/165 ,  H01L2224/08113 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/32245 ,  H01L2924/16195

摘要： A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

公开(公告)号：US12087664B2

公开(公告)日：2024-09-10

申请号：US18129061

申请日：2023-03-30

申请人： MEDIATEK INC.

发明人： Chia-Hao Hsu ,  Tai-Yu Chen ,  Sheng-Liang Kuo ,  Bo-Jiun Yang

IPC分类号： H01L23/473 ,  H01L23/00 ,  H01L23/16

CPC分类号： H01L23/473 ,  H01L23/16 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

摘要： A semiconductor package includes a substrate; a die mounted on a top surface of the substrate in a flip-chip fashion; and a lid mounted on the die and on a perimeter of the substrate. The lid includes a cover plate and four walls formed integral with the cover plate. A liquid-cooling channel is situated between the cover plate of the lid and a rear surface of the die for circulating a coolant relative to the semiconductor package.

公开(公告)号：US20240297087A1

公开(公告)日：2024-09-05

申请号：US18115840

申请日：2023-03-01

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Sheng-Kai CHANG ,  Chih-Kang Han ,  Leo Li ,  Lieh-Chuan Chen ,  Chien-Li Kuo

IPC分类号： H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/16 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L25/0655 ,  H01L21/563 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1011

摘要： A package module includes an interposer, a plurality of semiconductor dies on the interposer, a module stiffener on the interposer adjacent to the plurality of semiconductor dies, and a molding material layer on the interposer around the plurality of semiconductor dies and the module stiffener.

公开(公告)号：US12046523B2

公开(公告)日：2024-07-23

申请号：US16681539

申请日：2019-11-12

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Wen-Long Lu

IPC分类号： H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L25/00 ,  H01L25/16 ,  H01L21/683 ,  H01L23/00

CPC分类号： H01L23/16 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/66 ,  H01L25/16 ,  H01L25/50 ,  H01L21/6835 ,  H01L24/16 ,  H01L2223/6616 ,  H01L2224/16225 ,  H01L2924/3511

摘要： A semiconductor device package includes a substrate; an electronic component disposed on the substrate; multiple supporting structures disposed on the substrate; and a reinforced structure disposed on the supporting structures and extending in parallel with the substrate.

公开(公告)号：US20240222211A1

公开(公告)日：2024-07-04

申请号：US18091270

申请日：2022-12-29

申请人： Intel Corporation

发明人： Peumie Abeyratne Kuragama ,  Dilan Seneviratne ,  Whitney Bryks

IPC分类号： H01L23/16 ,  H01L23/00 ,  H01L23/15 ,  H01L23/538

CPC分类号： H01L23/16 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/562

摘要： IC device packages including a low-CTE polymer dielectric build-up material comprising a filler having a negative CTE. Low CTE build-up materials may have a CTE less than 10 ppm/K below the glass transition temperature (Tg) of the polymer resin containing the filler. With a negative CTE filler, polymer resin expansion during thermal cycles (e.g., resin cure) may be at least partially countered through negative thermal expansion of the filler.

公开(公告)号：US12027469B2

公开(公告)日：2024-07-02

申请号：US17500920

申请日：2021-10-13

申请人： Advanced Semiconductor Engineering, Inc.

发明人： En Hao Hsu ,  Kuo Hwa Tzeng ,  Chia-Pin Chen ,  Chi Long Tsai

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/16

CPC分类号： H01L23/562 ,  H01L23/16 ,  H01L23/3107 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/022 ,  H01L2224/02377 ,  H01L2224/13018

摘要： An electronic device package and manufacturing method thereof are provided. The electronic device package includes an electronic component including an active surface, a patterned conductive layer disposed on the active surface, an encapsulation layer disposed over the patterned conductive layer, and a buffer layer disposed between the patterned conductive layer and the encapsulation layer. The buffer layer is shaped and sized to alleviate a stress generated due to an interaction between the patterned conductive layer and the encapsulation layer.

公开(公告)号：US20240194544A1

公开(公告)日：2024-06-13

申请号：US18581213

申请日：2024-02-19

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Sang Jae Jang ,  Weilung Lu ,  Burt Barber ,  Adrian Arcedera ,  Shingo Nakamura

IPC分类号： H01L23/043 ,  H01L21/50 ,  H01L21/52 ,  H01L23/04 ,  H01L23/055 ,  H01L23/06 ,  H01L23/10 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L23/043 ,  H01L21/50 ,  H01L21/52 ,  H01L23/04 ,  H01L23/055 ,  H01L23/06 ,  H01L23/10 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49838

摘要： In one example, a semiconductor device comprises a substrate comprising a top side, a bottom side, and a conductive structure, a body over the top side of the substrate, an electronic component over the top side of the substrate and adjacent to the body, wherein the electronic component comprises an interface element on a top side of the electronic component, a lid over the interface element and a seal between the top side of the electronic component and the lid, and a buffer on the top side of the substrate between the electronic component and the body. Other examples and related methods are also disclosed herein.

公开(公告)号：US12009271B2

公开(公告)日：2024-06-11

申请号：US16511360

申请日：2019-07-15

申请人： Intel Corporation

发明人： Edvin Cetegen ,  Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Nicholas Neal ,  Sergio Chan Arguedas ,  Vipul Mehta

IPC分类号： H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

摘要： Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.