公开(公告)号：US20210050287A1

公开(公告)日：2021-02-18

申请号：US16543238

申请日：2019-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenivasan K. KODURI ,  Nazila DADVAND

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  C25D7/00

Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

公开(公告)号：US20220415768A1

公开(公告)日：2022-12-29

申请号：US17898656

申请日：2022-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey MORRONI ,  Rajeev Dinkar JOSHI ,  Sreenivasan K. KODURI ,  Sujan Kundapur MANOHAR ,  Yogesh K. RAMADASS ,  Anindya PODDAR

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.

公开(公告)号：US20180301404A1

公开(公告)日：2018-10-18

申请号：US15951021

申请日：2018-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey MORRONI ,  Rajeev Dinkar JOSHI ,  Sreenivasan K. KODURI ,  Sujan Kundapur MANOHAR ,  Yogesh K. RAMADASS ,  Anindya PODDAR

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/29 ,  H01L23/31

Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.

公开(公告)号：US20180301402A1

公开(公告)日：2018-10-18

申请号：US15950984

申请日：2018-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey MORRONI ,  Rajeev Dinkar JOSHI ,  Sreenivasan K. KODURI ,  Sujan Kundapur MANOHAR ,  Yogesh K. RAMADASS ,  Anindya PODDAR

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in which at least a portion of the passive component is disposed in a stacked arrangement.