公开(公告)号：US20250096768A1

公开(公告)日：2025-03-20

申请号：US18966299

申请日：2024-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya PODDAR ,  Hau NGUYEN ,  Masamitsu MATSUURA

IPC: H03H9/02 ,  H03H3/007 ,  H03H3/04 ,  H03H9/05 ,  H03H9/10 ,  H03H9/17 ,  H03H9/24

Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.

公开(公告)号：US20230396230A1

公开(公告)日：2023-12-07

申请号：US18454034

申请日：2023-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya PODDAR ,  Hau NGUYEN ,  Masamitsu MATSUURA

IPC: H03H9/02 ,  H03H9/05 ,  H03H9/10 ,  H03H9/17 ,  H03H9/24 ,  H03H3/007 ,  H03H3/04

CPC classification number: H03H9/02133 ,  H03H9/02102 ,  H03H9/02448 ,  H03H9/0523 ,  H03H9/0533 ,  H03H9/0547 ,  H03H9/1057 ,  H03H9/17 ,  H03H9/2426 ,  H03H9/2457 ,  H03H3/0073 ,  H03H3/04 ,  H03H9/1021 ,  H03H2003/0407

Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.

公开(公告)号：US20190206741A1

公开(公告)日：2019-07-04

申请号：US15858862

申请日：2017-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya PODDAR ,  Usman Mahmood CHAUDHRY ,  Tran Kiet THU ,  Mahmud Halim CHOWDHURY ,  Peter SMEYS

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/304 ,  H01L27/088 ,  H01L23/31

CPC classification number: H01L21/823481 ,  H01L21/3043 ,  H01L21/76224 ,  H01L21/823425 ,  H01L21/823487 ,  H01L23/3178 ,  H01L27/088

Abstract: In one aspect of the disclosure, an integrated circuit is disclosed. The integrated circuit includes a first FET device formed on a substrate having a first source, a first gate, and a first channel. The first channel is formed in the substrate, connecting the first source to a common drain. The integrated circuit also includes a second FET device formed on the substrate having a second source, a second gate, and a second channel. The second channel is formed in the substrate, connecting the second source to the common drain. A trench is formed in the substrate between the first channel and the second channel.

公开(公告)号：US20230036643A1

公开(公告)日：2023-02-02

申请号：US17390823

申请日：2021-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahmud Halim CHOWDHURY ,  Amin SIJELMASSI ,  Murali KITTAPPA ,  Anindya PODDAR ,  Honglin GUO ,  Joe Adam GARCIA ,  John Paul TELLKAMP

IPC: H01L23/00 ,  H01H85/02

Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

公开(公告)号：US20220069795A1

公开(公告)日：2022-03-03

申请号：US17002357

申请日：2020-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya PODDAR ,  Hau NGUYEN ,  Masamitsu MATSUURA

IPC: H03H9/02 ,  H03H9/05 ,  H03H9/10 ,  H03H9/17 ,  H03H9/24 ,  H03H3/007 ,  H03H3/04

Abstract: In examples, a device comprises a semiconductor die, a thin-film layer, and an air cavity positioned between the semiconductor die and the thin-film layer. The air cavity comprises a resonator positioned on the semiconductor die. A rib couples to a surface of the thin-film layer opposite the air cavity.

公开(公告)号：US20180301403A1

公开(公告)日：2018-10-18

申请号：US15951003

申请日：2018-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey MORRONI ,  Rajeev Dinkar JOSHI ,  Sreenivasan K. KODURI ,  Sujan Kundapur MANOHAR ,  Yogesh K. RAMADASS ,  Anindya PODDAR

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.

公开(公告)号：US20240332243A1

公开(公告)日：2024-10-03

申请号：US18740456

申请日：2024-06-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahmud Halim CHOWDHURY ,  Amin SIJELMASSI ,  Murali KITTAPPA ,  Anindya PODDAR ,  Honglin GUO ,  Joe Adam GARCIA ,  John Paul TELLKAMP

IPC: H01L23/00 ,  H01H85/02 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L24/48 ,  H01H85/0241 ,  H01L24/49 ,  H01L24/85 ,  H01H2085/0283 ,  H01L23/49555 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/4801 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/4846 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/49111 ,  H01L2224/494 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/8534 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/2064 ,  H01L2924/2075

Abstract: In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

公开(公告)号：US20230274993A1

公开(公告)日：2023-08-31

申请号：US17683253

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindya PODDAR ,  Amin SIJELMASSI ,  Hau NGUYEN ,  Kashyap MOHAN

IPC: H01L23/31 ,  H01L23/04

CPC classification number: H01L23/3121 ,  H01L23/04

Abstract: One example includes a method for fabricating an integrated circuit (IC) device. The method includes fabricating a semiconductor die comprising an IC. The method also includes patterning a film over a portion of the first surface of the semiconductor die. The method also includes attaching a second surface of the semiconductor die opposite the first surface to a substrate. The method further includes depositing molding material over the semiconductor die to cover at least the first surface of the semiconductor die.

公开(公告)号：US20220415768A1

公开(公告)日：2022-12-29

申请号：US17898656

申请日：2022-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey MORRONI ,  Rajeev Dinkar JOSHI ,  Sreenivasan K. KODURI ,  Sujan Kundapur MANOHAR ,  Yogesh K. RAMADASS ,  Anindya PODDAR

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.

公开(公告)号：US20210035932A1

公开(公告)日：2021-02-04

申请号：US17009664

申请日：2020-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki SADA ,  Shoichi IRIGUCHI ,  Genki YANO ,  Luu Thanh NGUYEN ,  Ashok PRABHU ,  Anindya PODDAR ,  Yi YAN ,  Hau NGUYEN

IPC: H01L23/00 ,  H01L21/78

Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.