公开(公告)号：US11290089B2

公开(公告)日：2022-03-29

申请号：US16934342

申请日：2020-07-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subrahmanya Bharathi Akondy ,  Nirav Ginwala

IPC: H03K7/08 ,  H03K5/04 ,  H03K3/017

Abstract: A circuit includes a base pulse generator to generate a first pulse width modulated (PWM) pulse, a first clock generation circuit to generate M clocks of a first frequency and phase-shifted with respect to each other, and a second clock generation circuit to receive the M clocks and to generate N clocks each at a second lower frequency and the M clocks are phase-shifted with respect to each other. Each of a plurality of flip-flops includes a clock input to receive a different one of the N clocks, a data input coupled to receive the first PWM pulse, and a flip-flop output. A selection circuit includes a plurality of inputs and a selection circuit output. Each of the plurality of inputs is coupled to a corresponding flip-flop output. The selection circuit provides, responsive to a control signal, a selected one of the flip-flop outputs as the selection circuit output.

公开(公告)号：US10361838B2

公开(公告)日：2019-07-23

申请号：US15662249

申请日：2017-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subrahmanya Bharathi Akondy

IPC: H04L7/00 ,  H04L12/407 ,  H04L25/49

Abstract: One example includes a master microcontroller in a communication interface system. The microcontroller includes a transmitter configured to generate a clock signal at a selected frequency and to provide the clock signal to a slave microcontroller on a two-wire communication cable during a clock learning mode. The transmitter can be further configured to provide master data signal requests at the selected frequency on the two-wire communication cable during a data transfer mode. The microcontroller also includes a receiver configured to receive slave data signals at the variable frequency via the two-wire communication cable in response to the master data signal requests during the data transfer mode.