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公开(公告)号:US20220157222A1
公开(公告)日:2022-05-19
申请号:US17526710
申请日:2021-11-15
Applicant: Texas Instruments Incorporated
Inventor: Yonghui Tang , Charles Michael Campbell , Mustafa Ulvi Erdogan , Douglas Edward Wente , Yanli Fan
IPC: G09G3/20
Abstract: An example apparatus includes: a first input and a second input, a first equalizer with a third input, a fourth input, and a fifth input, the third input coupled to the first input, the fourth input coupled to the second input, a second equalizer with a sixth input, a seventh input, and an eighth input, the sixth input coupled to the first input, the seventh input coupled to the second input, and a controller coupled to the fifth input and the eighth input.
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公开(公告)号:US11068428B2
公开(公告)日:2021-07-20
申请号:US16414496
申请日:2019-05-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing Maung , Yonghui Tang , Huanzhang Huang , Douglas Edward Wente
Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.
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公开(公告)号:US20170315946A1
公开(公告)日:2017-11-02
申请号:US15651432
申请日:2017-07-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Win Naing Maung , Yonghui Tang , Suzanne Mary Vining , Hao Liu
IPC: G06F13/38
CPC classification number: G06F13/385
Abstract: A signal conditioner can include a state machine configured to detect a predetermined protocol level mode of a data signal on a bi-directional serial bus. The signal conditioner can also include a re-driver configured to inject current into at least one of a rising edge and a falling edge of the data signal on the bi-directional serial bus in response to the detection of the predetermined protocol level mode.
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